Semiconductor package
A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.
1. A semiconductor package comprising:
a substrate;
a first semiconductor chip module attached to the substrate;
a conductive connection member attached to the first semiconductor chip module, the conductive connection member comprising a conductive plate, a via pattern, and connection members; and
a second semiconductor chip module attached to the conductive connection member,
wherein the first semiconductor chip module is disposed over the substrate,
the second semiconductor chip module is disposed over the first semiconductor chip module, and
the conductive connection member comprising the conductive plate, the via pattern, and the connection members, is interposed entirely between the first semiconductor chip module and the second semiconductor chip module.
2. The semiconductor package according to claim 1 , wherein the conductive connection member comprises:
the conductive plate;
the connection members placed between the conductive plate and the first semiconductor chip module and electrically connecting the conductive plate with the first semiconductor chip module; and
a spacer member interposed between the conductive plate and the first semiconductor chip module.
3. The semiconductor package according to claim 2 , wherein the conductive plate comprises a substrate having electrical connection patterns or a tape having electrical connection patterns.
4. The semiconductor package according to claim 1 , wherein the first semiconductor chip module comprises:
at least two first semiconductor chips stacked in a face-up configuration, the at least two first semiconductor chips being offset from each other in a step-like shape and having first bonding pads disposed on respective step surfaces; and
first connection members electrically connecting the first semiconductor chips with one another and electrically connecting a lowermost first semiconductor chip among the first semiconductor chips with the substrate.
5. The semiconductor package according to claim 1 , wherein the second semiconductor chip module comprises:
at least two second semiconductor chips stacked in a face-up configuration, the at least two second semiconductor chips being offset from each other in a step-like shape and having second bonding pads disposed on respective step surfaces; and
second connection members electrically connecting the second semiconductor chips with one another and electrically connecting a lowermost second semiconductor chip among the second semiconductor chips with the conductive connection member.
6. The semiconductor package according to claim 1 , further comprising:
an encapsulant formed to seal an upper surface of the substrate, the first and second semiconductor chip modules, and the conductive connection member; and
external connection terminals attached to a lower surface of the substrate.
7. A semiconductor package comprising:
a substrate; and
at least two package units stacked on the substrate,
each package unit comprising:
a first semiconductor chip module;
a conductive connection member attached to the first semiconductor chip module, the conductive connection member comprising a conductive plate, a via pattern, and connection members; and
a second semiconductor chip module attached to the conductive connection member,
wherein the first semiconductor chip module is disposed over the substrate,
the second semiconductor chip module is disposed over the first semiconductor chip module, and
the conductive connection member comprising the conductive plate, the via pattern, and the connection members, is interposed entirely between the first semiconductor chip module and the second semiconductor chip module.
8. The semiconductor package according to claim 7 , wherein the conductive connection member comprises:
the conductive plate;
the connection members placed between the conductive plate and the first semiconductor chip module and electrically connecting the conductive plate with the first semiconductor chip module; and
a spacer member interposed between the conductive plate and the first semiconductor chip module.
9. The semiconductor package according to claim 8 , wherein the conductive plate comprises a substrate having electrical connection patterns or a tape having electrical connection patterns.
10. The semiconductor package according to claim 7 , wherein the first semiconductor chip module comprises:
at least two first semiconductor chips stacked in a face-up configuration, the at least two first semiconductor chips being offset from each other in a step-like shape and having first bonding pads disposed on respective step surfaces; and
first connection members electrically connecting the first semiconductor chips with one another, and electrically connecting a lowermost first semiconductor chip among the first semiconductor chips with the substrate when the package unit is the lower package unit among at least two package units.
11. The semiconductor package according to claim 7 , wherein the second semiconductor chip module comprises:
at least two second semiconductor chips stacked in a face-up configuration in a step-like shape and having second bonding pads disposed on respective step surfaces; and
second connection members electrically connecting the second semiconductor chips with one another and electrically connecting a lowermost second semiconductor chip among the second semiconductor chips with the conductive connection member.
12. The semiconductor package according to claim 7 , further comprising:
an encapsulant formed to seal an upper surface of the substrate, the first and second semiconductor chip modules, and the conductive connection member; and
external connection terminals attached to a lower surface of the substrate.