IP Library Granted Patent US 8,816,409
Granted Patent B2
US 8,816,409 · App. 12/837,475 · Granted Aug 26, 2014

Metal-oxide semiconductor transistor

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Quick Facts
Patent No.
US 8,816,409
App. No.
12/837,475
Granted
Aug 26, 2014
Kind
B2
Abstract

A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Claims (11)

1. A metal-oxide semiconductor (MOS) transistor, comprising:

a semiconductor substrate including a shallow trench isolation;

a first photo-etched layer comprising a gate disposed on the semiconductor substrate,

wherein the gate comprises four sidewalls, and two of the four sidewalls opposite to each other comprise a spacer thereon while the other two sidewalls opposite to each other comprise no said spacer, wherein the gate is of a rectangular shape and has a second photo-etched slot directly formed on one sidewall of the gate and exposing the shallow trench isolation, of which no spacer is disposed thereon;

a recess in the semiconductor substrate adjacent two sides of the spacers; and

an epitaxial layer disposed in the recess in the semiconductor substrate adjacent to two sides of the spacer; and

wherein the second photo-etched slot is formed without a line end bridge.

2. The MOS transistor of claim 1 , wherein the spacer comprises a first spacer and a second spacer.

3. The MOS transistor of claim 2 , wherein each of the first spacer and the second spacer comprises silicon oxide and silicon nitride.

4. The MOS transistor of claim 1 , wherein the epitaxial layer comprises silicon germanium or silicon carbide.

5. The MOS transistor of claim 1 , wherein the slot is not on top of an active region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2010
From: WEI, MING-TE; WU, WEN-CHEN; KUO, LUNG-EN; TSAO, PO-CHAO
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 024694/0248 →