Method of manufacturing complementary metal oxide semiconductor device

1. A method of manufacturing a complementary metal oxide semiconductor (CMOS) device comprising steps of:

providing a substrate having a first region and a second region defined thereon;

forming a first gate structure and a second gate structure respectively in the first region and the second region, each of the gate structures comprising a gate dielectric layer, a sacrificial layer, and a hard mask layer;

forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure;

performing an etching process to form first recesses in the substrate at two sides of the second gate structure;

performing a selective epitaxial growth (SEG) process to form epitaxial silicon layers in each first recess;

forming a patterned second protecting layer to cover the entire second region and expose the entire first region; and

performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer in the first region to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure, and the first spacer in the second region and the hard mask layer on the second gate structure being protected from the dry etching process by the second patterned protecting layer.

2. The method of claim 1 further comprising a step of forming first type lightly-doped drains (LDDs) in the substrate and second type LDDs in the substrate.

3. The method of claim 2 further comprising a step of forming a seal layer on the substrate before forming the first type LDDs and the second type LDDs.

4. The method of claim 1 , wherein the step of forming a patterned first protecting layer and the first spacer further comprises:

forming a first protecting layer on the substrate; and

patterning the first protecting layer to form the patterned first protecting layer covering the first region and the first spacer on the sidewalls of the second gate structure.

5. The method of claim 4 , wherein the hard mask layer and the first protecting layer comprise a same material.

6. The method of claim 5 , wherein the same material comprises SiO, SiN, SiON, SiCN, SiC, SiOC, or silicon-rich-nitride (SRN).

7. The method of claim 1 , wherein a height deviation is formed between the first gate structure and the second gate structure after the etching process.

8. The method of claim 7 , wherein the drying etching process is performed to eliminate the height deviation.

9. The method of claim 1 , wherein at least a dopant is doped into the epitaxial silicon layers in situ with the SEG process to form a second type source/drain.

10. The method of claim 1 , further comprising a step of performing an ion implantation to form a first type source/drain with the patterned second protecting layer serving as an implant mask.

11. The method of claim 10 , further comprising steps of:

performing a self-aligned silicide (salicide) process to form salicide layers respectively on the first type source/drain and the epitaxial silicon layers; and

forming an interlayer dielectric (ILD) layer on the substrate.

12. The method of claim 11 , further comprising steps of:

performing a planarization process to remove a portion of the ILD layer and the hard mask layer;

removing the sacrificial layer to form second recesses respectively in the first region and the second region; and

forming a first type metal gate and a second type metal gate respectively in the second recesses in the first region and the second region.