Vertical channel transistor array and manufacturing method thereof
View Patent ↗A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts.
1. A vertical channel transistor array comprising:
a plurality of semiconductor pillars disposed in a semiconductor substrate and arranged in a row/column array, wherein each of the semiconductor pillars forms an active region of the vertical channel transistor array;
a plurality of embedded bit lines filled in a plurality of trenches in the semiconductor substrate, which are arranged in parallel in the semiconductor substrate and extended along a column direction;
a plurality of bit line contacts, each of the bit line contacts being disposed on a side surface of one of the embedded bit lines and contacted with a side surface of a semiconductor pillar, wherein the embedded bit lines are electrically connected to the semiconductor pillars located in a same column through the bit line contacts;
a plurality of embedded word lines filled in a plurality of trenches in the semiconductor substrate, which are arranged in parallel above the embedded bit lines and extended along a row direction, wherein the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars; and
a current leakage isolation structure disposed at terminals of the embedded bit lines to prevent current leakage between adjacent bit line contacts.
2. The vertical channel transistor array as claimed in claim 1 , wherein the current leakage isolation structure is a shallow trench isolation structure.
3. The vertical channel transistor array as claimed in claim 2 , wherein the shallow trench isolation structure comprises a plurality of shallow trench isolation blocks.
4. The vertical channel transistor array as claimed in claim 1 , wherein the current leakage isolation structure is a doped region.
5. The vertical channel transistor array as claimed in claim 1 , wherein each of the embedded word lines is connected to a first side and a second side of one of the semiconductor pillars located in the same row, and the first side is opposite to the second side.
6. The vertical channel transistor array as claimed in claim 1 further comprising a current leakage isolation doped region disposed in the semiconductor substrate located below the embedded bit lines to prevent the adjacent bit line contacts from generating current leakage at bottoms of the embedded bit lines.
7. The vertical channel transistor array as claimed in claim 1 , wherein each of the embedded bit lines comprises a barrier layer and a conductive layer.
8. The vertical channel transistor array as claimed in claim 1 further comprising an insulating layer disposed between each of the embedded bit lines and the semiconductor substrate.
9. The vertical channel transistor array as claimed in claim 1 , wherein a material of the embedded bit lines comprises silicide.