Tiered integrated circuit assembly and a method for manufacturing the same
View Patent ↗A tiered integrated circuit (IC) assembly includes stacks of a limited number of ICs coupled to each other and arranged in a first direction across a base tier and a second tier. The base tier includes ICs and a data bridge. Each of the ICs includes a respective array of through silicon vias (TSVs) arranged in parallel with the first direction. The data bridge includes submicron metal interconnects (densely spaced electrical conductors) arranged in a plane that is substantially orthogonal to the first direction. The second tier is adjacent to the base tier and includes respective high-performance ICs different from the ICs of the base tier. The TSVs provide power and ground paths to the ICs in the second tier. In an example embodiment, the ICs in the second tier support one or more data bridges for connecting adjacent stacks.
1. A tiered assembly of integrated circuits (ICs), comprising:
a base tier including a first set of ICs and a data bridge, the ICs each having a respective array of through silicon vias (TSVs), the data bridge having submicron metal interconnects arranged in a plane that is substantially orthogonal to a longitudinal axis of the TSVs; and
a second tier adjacent to the base tier, the second tier including a second set of ICs, different from the first set of ICs, at least two members of the second set of ICs coupled to each other by the data bridge, the submicron metal interconnects of the data bridge providing an interconnect density and signal integrity between the second set of ICs coupled by the data bridge that is substantially similar to that provided by internal connections in the second set of ICs, wherein the second set of ICs generate thermal energy at a rate that requires an external thermal transfer element to maintain thermal equilibrium within the respective members of the second set of ICs.
2. The assembly of claim 1 , wherein respective major surfaces of the first set of ICs and the data bridge are substantially parallel.
3. The assembly of claim 2 , wherein adjacent members of the first set of ICs are separated from each other by the data bridge.
4. The assembly of claim 1 , wherein the first set of ICs comprises circuits that in operation generate thermal energy at a rate that results in thermal equilibrium within the respective members of the first set of ICs in the absence of a thermal transfer element.
5. The assembly of claim 1 , wherein the first set of ICs comprises one or more of a memory element, a bypass capacitor, a power regulating transistor, and an electrostatic discharge protector.
6. The assembly of claim 1 , wherein the submicron metal interconnects are made with technology similar to that used in making the second set of ICs.
7. The assembly of claim 1 , wherein the submicron metal interconnects include at least one arranged with an angle.
8. The assembly of claim 1 , wherein the base tier further comprises a third set of ICs, the third set of ICs coupled to corresponding members of the second set of ICs.
9. The assembly of claim 8 , wherein the third set of ICs electrically support an optical device.
10. The assembly of claim 8 , wherein a member of the third set of ICs is coupled to a member of the second set of ICs by submicron metal interconnects arranged in a plane that is substantially orthogonal to a longitudinal axis of the TSVs.
11. The assembly of claim 1 , further comprising:
a third tier adjacent to the second tier and removed from the base tier, the third tier comprising a thermal transfer element.
12. The assembly of claim 11 , wherein the thermal transfer element comprises a heat sink.
13. The assembly of claim 11 , wherein the thermal transfer element comprises a silicon platen.
14. The assembly of claim 1 , further comprising:
a power interface tier adjacent to the base tier and removed from the second tier, the power interface tier including a respective connection that provides a supply voltage from an external source to each member of the second set of ICs by way of the TSVs in the first set of IC devices.
15. The assembly of claim 14 , wherein the power interface tier comprises a silicon support structure with TSVs arranged in registration with corresponding TSVs of the first set of ICs.
16. A tiered integrated circuit (IC) assembly, comprising:
a first tier including a first set of ICs and a data bridge, the first set of ICs each having a respective array of through silicon vias (TSVs), the data bridge including submicron metal interconnects arranged near a surface of the data bridge; and
a second tier adjacent to the first tier, the second tier including a second set of ICs that generate thermal energy at a rate that requires an external thermal transfer element to maintain thermal equilibrium, adjacent members of the second set of ICs coupled to one another by the data bridge, the submicron metal interconnects of the data bridge providing an interconnect density and signal integrity between the second set of ICs coupled by the data bridge that is substantially similar when compared to the interconnect density and signal integrity provided by internal connections in the second set of ICs, the data bridge being supported along at least two edges by the adjacent members of the second set of ICs.
17. The assembly of claim 16 , further comprising:
respective connectors coupled to each member of the first set of ICs; and
a silicon structure directly supporting the second tier.
18. The assembly of claim 16 , further comprising:
wherein the second tier further comprises a third set of ICs that electrically support a respective optical device; and
a second data bridge between a member of the third set of ICs and an adjacent member of the second set of ICs, the second data bridge providing data signals in a direction that is substantially orthogonal to a longitudinal axis of the TSVs.