IP Library Granted Patent US 8,415,193
Granted Patent B2
US 8,415,193 · App. 12/840,622 · Granted Apr 9, 2013

Method for manufacturing solid state image forming device, and solid state image forming device

Inventor: Hajime Ootake (Kanagawa-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,415,193
App. No.
12/840,622
Granted
Apr 9, 2013
Kind
B2
Abstract

A method for manufacturing a solid state image forming device according to an embodiment includes forming a transparent resin layer 20 on a semiconductor substrate 11 , having a plurality of photodiode layers 12 formed thereon in a lattice, through R, G, and B color filters that are formed according to a Bayer arrangement; forming a plurality of first microlens mother dies 23 on the transparent resin layer 20 at the positions corresponding to the green color filters G in such a manner that the outer peripheries thereof are separated from each other; forming a plurality of second microlens mother dies 24 in such a manner that they are formed to fill the gap between the first microlens mother dies 23 and the outer peripheries thereof are separated from each other; and etching the transparent resin layer 20 with the plurality of first microlens mother dies 23 and the plurality of second microlens mother dies 24 being used as masks.

Claims (31)

1. A method for manufacturing a solid state image forming device comprising:

forming a transparent resin layer on a first surface of a semiconductor substrate having a plurality of photodiode layers formed thereon in a lattice;

forming a plurality of first microlens mother die materials on the transparent resin layer so as to be arranged checkerwise corresponding to the positions of the plurality of photodiode layers and to be separated from each other;

forming a plurality of first microlens mother dies so as to be separated from each other, wherein the plurality of first microlens mother dies are formed by a heat treatment of the plurality of first microlens mother die materials;

forming a plurality of second microlens mother die materials in such a manner that they are arranged between the plurality of first microlens mother dies respectively, and are overlapped with outer peripheries of the plurality of first microlens mother dies in horizontal and vertical directions with respect to a lattice arrangement of the plurality of photodiode layers and are separated from each other in a diagonal direction with respect to the lattice arrangement;

forming a plurality of second microlens mother dies so as to be overlapped with outer peripheries of the plurality of first microlens mother dies in the horizontal and vertical directions and separated from each other in the diagonal direction, wherein said plurality of second microlens mother dies are formed by a heat treatment of the plurality of second microlens mother die materials; and

forming a plurality of first microlenses and a plurality of second microlenses by etching the transparent resin layer by using the plurality of first microlens mother dies and the plurality of second microlens mother dies as masks, wherein

the transparent resin layer is etched so that the plurality of first microlenses and the plurality of second microlenses which are formed are in contact with each other.

2. A method for manufacturing a solid state image forming device according to claim 1 , wherein

the planar shapes of the plurality of photodiode layers and a plurality of color filters stacked thereon in a section parallel to the surface of the semiconductor substrate are square, and the planar shapes of the first and second microlens mother die materials in a section parallel to the surface of the semiconductor substrate are polygonal.

3. A method for manufacturing a solid state image forming device according to claim 2 , wherein

the plurality of first and second microlens mother die materials are made of a photosensitive thermosetting resin.

4. A method for manufacturing a solid state image forming device according to claim 3 , wherein

the transparent resin layer or a planarizing layer is formed on the first surface of the semiconductor substrate, and a wiring layer is formed on a second surface of the semiconductor substrate.

5. A method for manufacturing a solid state image forming device according to claim 3 , wherein

a wiring layer is formed on the first surface of the semiconductor substrate, and the transparent resin layer or a planarizing layer is formed on the wiring layer of the semiconductor substrate.

6. A method for manufacturing a solid state image forming device comprising:

forming a planarizing layer on a first surface of a semiconductor substrate having a plurality of photodiode layers formed thereon in a lattice;

forming a plurality of first microlenses and a plurality of second microlenses from first and second microlens materials, respectively, on the planarizing layer so as to be arranged checkerwise corresponding to the positions of the plurality of photodiode layers;

after the plurality of first microlenses and the plurality of second microlenses are formed, forming a plurality of third microlens materials so as to be arranged at every other gap among the plurality of gaps formed between the plurality of first microlenses and the plurality of second microlenses, and to be overlapped with outer peripheries of the plurality of first microlenses and outer peripheries of the plurality of second microlenses in a horizontal and vertical directions with respect to a lattice arrangement of the plurality of photodiode layers;

forming plurality of third microlenses so as to be overlapped with outer peripheries of the plurality of first microlenses and outer peripheries of the plurality of second microlenses in the horizontal and vertical directions, wherein the plurality of third microlenses are formed by a heat treatment of the plurality of third microlens materials;

after the plurality of third microlenses are formed, forming a plurality of fourth microlens materials so as to be arranged at gaps, among the plurality of gaps formed between the plurality of first microlenses and the plurality of second microlenses, where the third microlenses are not formed, and to be overlapped with outer peripheries of the plurality of first microlenses and outer peripheries of the plurality of second microlenses in the horizontal and vertical directions and to be separated from the plurality of third microlenses in a diagonal direction with respect to the lattice arrangement; and

forming a plurality of fourth microlenses so as to be overlapped with outer peripheries of the plurality of first microlenses and outer peripheries of the plurality of second microlenses in the horizontal and vertical directions and to be in contact with outer peripheries of the plurality of third microlenses in the diagonal direction, wherein the plurality of fourth microlenses are formed by a heat treatment of the plurality of fourth microlens materials.

7. A method for manufacturing a solid state image forming device according to claim 6 , wherein

the planar shapes of the plurality of photodiode layers and color filters stacked thereon in a section parallel to the surface of the semiconductor substrate are square, the planar shapes of the first to fourth microlens materials in a section parallel to the surface of the semiconductor substrate are polygonal, and the planar shapes of the first to fourth microlenses formed by heat treating the first to fourth microlens materials in a section parallel to the surface of the semiconductor substrate are substantially circular.

8. A method for manufacturing a solid state image forming device according to claim 7 , wherein

the plurality of first to fourth microlens materials are made of a photosensitive thermosetting resin.

9. A method for manufacturing a solid state image forming device according to claim 6 , wherein

the planarizing layer is formed on the first surface of the semiconductor substrate, and a wiring layer is formed on a second surface of the semiconductor substrate.

10. A method for manufacturing a solid state image forming device according to claim 6 , wherein

a wiring layer is formed on the first surface of the semiconductor substrate, and the planarizing layer is formed on the wiring layer of the semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2010
From: OOTAKE, HAJIME
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024720/0974 →
Priority Claims (1)
JP 2009-171477 · Jul 22, 2009 · national
Continuity (1)
Related Publication 20110018080A1 · Jan 27, 2011