Semiconductor device with buried bit lines and method for fabricating the same

1. A method for fabricating a semiconductor device, comprising:

forming a plurality of trenches by etching a semiconductor substrate;

forming a plurality of buried bit lines each filling a portion of each trench;

forming a conductive layer gap-filling upper portions of the plurality of the buried bit lines;

forming a plurality of active pillars by simultaneously etching the conductive layer and the semiconductor substrate;

forming a plurality of vertical gates each surrounding each active pillar; and

forming a plurality of word lines coupling neighboring vertical gates with each other.

2. The method of claim 1 , further comprising:

forming an ohmic contact layer over the plurality of the buried bit lines.

3. The method of claim 2 , wherein the forming the ohmic contact layer comprises:

forming a metal silicide layer on a surface of the semiconductor substrate including the plurality of the buried bit lines, wherein a portion of the metal silicide layer formed over the plurality of the buried bit lines is thicker than a portion of the metal silicide layer on sidewalls of each trench; and

leaving the metal silicide layer on the plurality of the buried bit lines by selectively etching the metal silicide layer.

4. The method of claim 1 , wherein the plurality of the active pillars are formed in upper portions of the plurality of the buried bit lines.

5. The method of claim 1 , wherein the forming the plurality of the buried bit lines comprises:

forming a barrier layer over the semiconductor substrate including the plurality of the trenches;

forming a metal layer over the barrier layer until the plurality of the trenches are filled;

forming the plurality of the buried bit lines by performing an etch-back process onto the metal layer; and

performing an etch-back process onto the barrier layer until a surface of the plurality of the buried bit lines is exposed.

6. The method of claim 1 , wherein the forming the conductive layer comprises:

performing an epitaxial growth on both sidewalls of each of the plurality of the trenches exposed by the plurality of the buried bit lines.

7. The method of claim 6 , further comprising:

performing a planarization process onto the surface of the semiconductor substrate after the forming the conductive layer.

8. The method of claim 1 , wherein the forming the plurality of the trenches comprises:

forming a plurality of first trenches by performing a primary etch process onto the semiconductor substrate; and

forming a plurality of second trenches having a longer line width than the plurality of the first trenches by performing a secondary etch process onto the semiconductor substrate under the plurality of the first trenches.

9. The method of claim 8 , wherein the plurality of the buried bit lines are formed to fill the plurality of the second trenches.

10. The method of claim 1 , further comprising:

forming an inter-layer dielectric layer over a substrate structure including the plurality of the active pillars before the forming the plurality of the vertical gates; and

recessing the inter-layer dielectric layer by sequentially performing an etch-back process and a wet etch process.

11. The method of claim 10 , wherein the forming the plurality of the vertical gates comprises:

forming a gate conductive layer over the substrate structure including the plurality of the active pillars; and

performing an etch-back process onto the gate conductive layer.

12. The method of claim 1 , wherein the forming the plurality of the word lines comprises:

forming a metal layer over a substrate structure including the plurality of the vertical gates;

performing an etch-back process onto the metal layer; and

etching the metal layer which is etched back in a direction crossing the plurality of the buried bit lines.