IP Library Granted Patent US 8,081,011
Granted Patent B2
US 8,081,011 · App. 12/843,139 · Granted Dec 20, 2011

Method and apparatus for regulating a power supply of an integrated circuit

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Quick Facts
Patent No.
US 8,081,011
App. No.
12/843,139
Granted
Dec 20, 2011
Kind
B2
Abstract

Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Claims (87)

1. An integrated circuit (IC) comprising:

an input node configured to receive a power supply voltage generated by an external power supply circuit;

a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC; and

an interface circuit configured to produce a voltage control signal based on the interface control signal, wherein the power supply circuit generates the power supply voltage based on the voltage control signal, wherein:

said interface circuit comprises a plurality of switches, and

the interface control signal from the PVT detector controls said switches.

2. The circuit of claim 1 , wherein the interface circuit is configured to produce the voltage control signal by adjusting a resistance as a function of the interface control signal.

3. The circuit of claim 2 , wherein the resistance is an input resistance of a terminal of the IC.

4. The circuit of claim 1 , wherein said interface circuit comprises a first plurality of resistors, each connected to a corresponding one of said switches.

5. The circuit of claim 4 , wherein a terminal on the IC is connected to a maximum voltage through at least one of the first plurality of resistors when its corresponding switch is closed.

6. The circuit of claim 4 , wherein said interface circuit comprises a second plurality of resistors, each connected to a corresponding one of the switches.

7. The circuit of claim 6 , wherein a terminal on the IC is connected to a minimum voltage (e.g., ground) through at least one of the second plurality of resistors when its corresponding switch is closed.

8. The circuit of claim 1 , wherein the interface circuit comprises at least one active element configured to operate in a triode region.

9. The circuit of claim 1 , wherein the PVT detector comprises:

an oscillator that is configured to produce an oscillating signal that is a function of at least one of process, voltage, and temperature of the oscillator;

a converter connected to the oscillator and configured to convert the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit configured to produce the interface control signal based on the converted signal.

10. A method of controlling a power supply voltage provided by an external power supply circuit to an IC, the method comprising:

an input node of the IC receiving the power supply voltage;

a PVT detector generating an interface control signal based on at least one of process, voltage, and temperature of the IC; and

an interface circuit producing a voltage control signal based on the interface control signal, wherein:

the power supply circuit generates the power supply voltage based on the voltage control signal, and

producing the voltage control signal comprises adjusting the resistance of the interface circuit.

11. The method of claim 10 , wherein the resistance is an input resistance of a terminal of the IC.

12. The method of claim 10 , wherein adjusting the resistance of the interface circuit comprises connecting at least one resistor to one of a maximum voltage and a minimum voltage in response to the interface control signal.

13. The method of claim 10 , wherein adjusting the resistance of the interface circuit comprises controlling the resistance of at least one active element operating in a triode region in response to the interface control signal.

14. The method of claim 10 , wherein said generating an interface control signal comprises:

an oscillator producing an oscillating signal that is a function of at least one of process, voltage, and temperature of the oscillator;

a converter converting the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit producing the interface control signal based on said converted signal.

15. An integrated circuit (IC) comprising:

a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC;

an interface circuit configured to produce a voltage control signal based on the interface control signal; and

a power supply circuit configured to produce a maximum power supply voltage for the IC based on the voltage control signal,

wherein the interface circuit is configured to produce the voltage control signal by adjusting a resistance as a function of the interface control signal.

16. The circuit of claim 15 , wherein said PVT detector comprises:

an oscillator that is configured to produce an oscillating signal;

a converter connected to the oscillator and configured to convert the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit configured to produce the interface control signal based on the converted signal.

17. A method of controlling a positive supply voltage of an integrated circuit (IC), the method comprising:

a PVT detector generating an interface control signal based on at least one of process, voltage, and temperature of the IC;

an interface circuit producing a voltage control signal based on the interface control signal; and

a power supply circuit located on the IC producing the positive supply voltage for the IC based on the voltage control signal, wherein producing the voltage control signal comprises adjusting the resistance of the interface circuit.

18. The method of claim 17 , wherein generating the interface control signal comprises:

an oscillator producing an oscillating signal that is a function of at least one of process, voltage, and temperature of the oscillator;

a converter converting the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit producing an output control signal based on said converted signal.

19. A power supply circuit, comprising:

a resistive voltage divider comprising a first resistor connected to a second resistor at a first node;

a voltage regulator having a voltage-control input connected to said first node and configured to generate a power supply voltage as a function of a voltage level at the voltage-control input;

a terminal configured to receive a voltage control signal from an external circuit, said terminal being connected to the first node such that the voltage level at the voltage control input is based on the voltage control signal.

20. An integrated circuit (IC) comprising:

an input node configured to receive a power supply voltage generated by an external power supply circuit;

a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC; and

an interface circuit configured to produce a voltage control signal based on the interface control signal, wherein:

the power supply circuit generates the power supply voltage based on the voltage control signal, and

the interface circuit is configured to produce the voltage control signal by adjusting a resistance as a function of the interface control signal.

21. The circuit of claim 20 , wherein the resistance is an input resistance of a terminal of the IC.

22. An integrated circuit (IC) comprising:

an input node configured to receive a power supply voltage generated by an external power supply circuit;

a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC; and

an interface circuit configured to produce a voltage control signal based on the interface control signal, wherein the interface circuit comprises at least one active element configured to operate in a triode region.

23. An integrated circuit (IC) comprising:

an input node configured to receive a power supply voltage generated by an external power supply circuit;

a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC; and

an interface circuit configured to produce a voltage control signal based on the interface control signal,

wherein the PVT detector comprises:

an oscillator that is configured to produce an oscillating signal that is a function of at least one of process, voltage, and temperature of the oscillator;

a converter connected to the oscillator and configured to convert the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit configured to produce the interface control signal based on the converted signal.

24. A method of controlling a power supply voltage provided by an external power supply circuit to an IC, the method comprising:

an input node of the IC receiving the power supply voltage;

a PVT detector generating an interface control signal based on at least one of process, voltage, and temperature of the IC; and

an interface circuit producing a voltage control signal based on the interface control signal, wherein:

the power supply circuit generates the power supply voltage based on the voltage control signal, and

said generating an interface control signal comprises:

an oscillator producing an oscillating signal that is a function of at least one of process, voltage, and temperature of the oscillator;

a converter converting the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit producing the interface control signal based on said converted signal.

25. An integrated circuit (IC) comprising:

a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC;

an interface circuit configured to produce a voltage control signal based on the interface control signal; and

a power supply circuit configured to produce a maximum power supply voltage for the IC based on the voltage control signal,

wherein said PVT detector comprises:

an oscillator that is configured to produce an oscillating signal;

a converter connected to the oscillator and configured to convert the oscillating signal to a converted signal comprising one of a voltage signal and a current signal; and

a control circuit configured to produce the interface control signal based on the converted signal.

Assignments (12)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
CERTIFICATE OF CONVERSION Recorded Aug 29, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 033663/0948 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2010
From: AZIMI, KOUROS; MOBIN, MOHAMMAD S.; SHEETS, GREGORY W.; SMITH, LANE A.
To: AGERE SYSTEMS INC.
Reel/Frame 024851/0413 →