IP Library › Granted Patent US 9,024,431
Granted Patent B2
US 9,024,431 · App. 12/846,214 · Granted May 5, 2015

Semiconductor die contact structure and method

Inventors: Chung-Shi Liu (Hsin-Chu, TW); Chen-Hua Yu (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/5329H01L24/10H01L24/13H01L23/53228H01L2224/13099H01L2224/16H01L2924/01013H01L2924/01022H01L2924/01029H01L2924/01032H01L2924/01033H01L2924/01046H01L2924/01073H01L2924/01074H01L2924/01075H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/19041H01L2924/01006H01L2924/01019H01L2924/01024H01L2924/01047H01L2924/014
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Quick Facts
Patent No.
US 9,024,431
App. No.
12/846,214
Granted
May 5, 2015
Kind
B2
Abstract

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

Claims (36)

1. A semiconductor device comprising:

a substrate comprising a plurality of dielectric layers and conductive layers;

a metal contact in physical connection with an uppermost one of the plurality of conductive layers, the metal contact having a constant composition and a thickness greater than about 15,000 Å;

a first passivation layer over the metal contact;

a contact pad extending through the first passivation layer to make physical contact with the metal contact, the contact pad having a smaller width than the metal contact;

a second passivation layer over and in contact with a top surface of the contact pad; and

a connector in electrical connection with the metal contact.

2. The semiconductor device of claim 1 , wherein the connecter is a conductive pillar.

3. The semiconductor device of claim 2 , further comprising a post-passivation interconnect connecting the metal contact with the conductive pillar.

4. The semiconductor device of claim 3 , wherein the post-passivation interconnect comprises aluminum.

5. The semiconductor device of claim 1 , wherein the contact pad comprises aluminum.

6. The semiconductor device of claim 1 , wherein the connector is located directly over the metal contact.

7. The semiconductor device of claim 1 , wherein the connector is in direct contact with the metal contact.

8. The semiconductor device of claim 1 , wherein the connector is a solder bump.

9. A semiconductor device comprising:

a substrate comprising a plurality of metal layers;

a metal contact sharing an interface with the uppermost one of the plurality of metal layers, wherein the metal contact comprises a first region with a first material throughout the first region, the first region having a thickness greater than about 15,000 Å;

a first passivation layer over the metal contact;

a contact pad in physical connection with the metal contact and extending in a direction parallel with a major surface of the substrate no further than the metal contact;

a second passivation layer over the metal contact and the contact pad; and

a conductive pillar in electrical contact with the metal contact.

10. The semiconductor device of claim 9 , wherein the conductive pillar is a copper pillar.

11. The semiconductor device of claim 9 , wherein the metal contact comprises copper.

12. The semiconductor device of claim 9 , wherein the contact pad comprises aluminum.

13. The semiconductor device of claim 9 , wherein the metal contact has a thickness greater than about 20,000 Å.

14. The semiconductor device of claim 9 , wherein the metal contact is underlying and in direct contact with the conductive pillar.

15. The semiconductor device of claim 9 , further comprising a post-passivation interconnect connecting the metal contact with the conductive pillar.

16. The semiconductor device of claim 15 , wherein the post-passivation interconnect comprises aluminum.

17. A semiconductor device comprising:

a plurality of metal layers over a substrate;

a metal contact in physical contact with a conductive region of the plurality of metal layers, the metal contact having a single metal with a thickness greater than about 15,000 Å;

a first passivation layer over the metal contact;

a contact pad at least partially over the first passivation layer and in physical contact with the metal contact, the contact pad having a first width and the metal contact having a second width greater than the first width; and

a second passivation layer over the contact pad;

a conductive pillar in electrical contact with the metal contact.

18. The semiconductor device of claim 17 , wherein the metal contact comprises copper.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2010
From: LIU, CHUNG-SHI; YU, CHEN-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024761/0925 →
Continuity (2)
Provisional Application 61256187 · Oct 29, 2009
Related Publication 20110101520A1 · May 5, 2011