Method for manufacturing semiconductor device with buried gates
A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operational gate and a dummy gate. A height of a gate electrode layer (conductive material) of the dummy gate is formed to be lower than that of a gate electrode layer of the operational gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the dummy gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.
1. A method for manufacturing a semiconductor device, the method comprising:
forming a device isolation region that defines an active region in a semiconductor substrate;
etching the semiconductor substrate to form a gate region having a first recess and a second recess;
depositing a conductive material over the gate region and within the first and second recesses; to form a including an active gate in the first recess and a dummy gate in the second recess;
etching the conductive material provided in the second recess while preventing the conductive material provided in the first recess from being etched;
etching the conductive material provided in the first and second recesses; and
depositing an insulating film over the semiconductor substrate and the conductive material within the first and second recesses,
wherein the conductive material in the first recess defines an active gate and the conductive material in the second recess defines a dummy gate.
2. The method according to claim 1 , wherein the active region has a line pattern, and
wherein the dummy gate has a lower height than the active gate, the dummy gate being configured to be maintained at an off state.
3. The method according to claim 1 , wherein the conductive material includes any of polysilicon, aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN) and a combination thereof.
4. The method according to claim 1 , wherein the etching-the-semiconductor-substrate-to-form-a-gate-region step includes performing an anisotropic etch on the semiconductor substrate.
5. The method according to claim 1 , wherein the etching-the-conductive-material-provided-in-the-second-recess step and the etching-the-conductive-material-provided-in-the-first-and-second-recesses step are anisotropic etch steps, and
wherein the etching-the-conductive-material-provided-in-the-second-recess step is performed before the etching-the-conductive-material-provided-in-the-first-and-second-recesses step.
6. The method according to claim 1 , further comprising:
performing a chemical mechanical polishing (CMP) on the insulating film to expose the active region,
wherein the etching-the-conductive-material-provided-in-the-second-recess step is performed after the etching-the-conductive-material-provided-in-the-first-and-second-recesses step.
7. The method according to claim 1 , wherein the active gate and the dummy have a line pattern.
8. The method according to claim 1 , wherein the height of the dummy gate is smaller than that of the active gate.
9. The method according to claim 1 , further comprising:
implanting N-type impurities into the active region to form an N-type junction at a side of the active gate.
10. A method for manufacturing a semiconductor device, the method comprising:
forming a device isolation region that defines an active region in a semiconductor substrate;
etching the semiconductor substrate to form a first recess and a second recess;
depositing a conductive material within the first recess and the second recess;
performing a first etch step to etch the conductive material in the first recess and the second recess;
performing a second etch step to etch the conductive material of the second recess without etching the conductive material in the first recess; and
depositing an insulating film over the semiconductor substrate and within the first and second recesses,
wherein the conductive material in the first recess defines an active gate and the conductive material in the second recess defines a dummy gate that is maintained at an off state, and
wherein the dummy gate is provided with a height that is less than that of the active gate.
11. The method according to claim 10 , wherein the conductive material includes any of polysilicon, aluminum (Al), tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN) and a combination thereof.
12. The method according to claim 10 , wherein the first etch step is performed before the second etch step.
13. The method according to claim 10 , wherein the first and second etch steps are anisotropic etch steps.
14. The method according to claim 10 , wherein the active gate and the dummy gate have a line pattern.
15. The method according to claim 10 , wherein the second etch step is performed before the first etch step.
16. The method according to claim 10 , further comprising:
performing a chemical mechanical polishing (CMP) on the insulating film to expose the active region.