Semiconductor integrated circuit and method of testing circuit

1. A semiconductor integrated circuit comprising:

a ladder resistor configured to include a plurality of resistors series-connected to each other and be supplied with a correction voltage at least one of both ends of said series connection and a plurality of connection points in said series connection to generate a plurality of gradation voltages at said plurality of connection points;

a ROM decoder configured to select one of said plurality of gradation voltages generated by said ladder resistor, based on a supplied data signal; and

a test circuit configured to measure a leakage current in said ROM decoder,

wherein said test circuit includes:

a plurality of separation units configured to separate said series connection, which is respectively supplied with different power source voltages at both ends, at a certain portion, when said leakage current is measured, and

a control unit configured to control separation of said plurality of separation unit corresponding to said data signal.

2. The semiconductor integrated circuit according to claim 1 , wherein said plurality of separation units is a plurality of switches provided between every adjacent two of said plurality of resistors.

3. The semiconductor integrated circuit according to claim 2 , wherein said control unit controls one of said plurality of separation units to be in a separation state and the others of said plurality of separation units to be in a connection state, when said leakage current is measured.

4. The semiconductor integrated circuit according to claim 3 , wherein said test circuit further includes:

a plurality of suppliers configured to be provided correspondingly to said plurality of separation units, and control supply of said different power source voltages to resistors in said plurality of resistors connected to both sides of a separating portion that separates said series connection.

5. The semiconductor integrated circuit according to claim 4 , wherein each of said plurality of suppliers includes:

a first supply switch configured to be provided between a first power source as one of said different power source voltages and said separating portion, and

a second supply switch configured to be provided between a second power source as the other of said different power source voltages,

wherein said control unit controls said first supply switch and said second supply switch.

6. The semiconductor integrated circuit according to claim 5 , wherein said ROM decoder includes:

enhancement type transistors and depletion type transistors configured to be arranged in a matrix,

wherein each row of said matrix includes:

a transistor series circuit configured to be provided with a plurality of pairs, each pair being composed of two transistors, one being an enhancement type transistor and the other being a depletion type transistor that are adjacent to each other,

wherein one end of said transistor series circuit is connected to corresponding one of said plurality of connection points of said ladder resistor, and

the other end of said transistor series circuit is mutually connected to the other ends of the other transistor series circuits in the other rows to be connected to a post-stage circuit,

wherein gates of enhancement type transistors and depletion type transistors included in each column of said matrix are mutually connected, and

said data signal is supplied to gates of odd-numbered columns of said matrix, and an inversion signal of said data signal is supplied to gates of even-numbered columns of said matrix.

7. The semiconductor integrated circuit according to claim 1 , wherein said control unit controls one of said plurality of separation units to be in a separation state and the others of said plurality of separation units to be in a connection state, when said leakage current is measured.

8. The semiconductor integrated circuit according to claim 7 , wherein said test circuit further includes:

a plurality of suppliers configured to be provided correspondingly to said plurality of separation units, and control supply of said different power source voltages to resistors in said plurality of resistors connected to both sides of a separating portion that separates said series connection.

9. The semiconductor integrated circuit according to claim 8 , wherein each of said plurality of suppliers includes:

a first supply switch configured to be provided between a first power source as one of said different power source voltages and said separating portion, and

a second supply switch configured to be provided between a second power source as the other of said different power source voltages,

wherein said control unit controls said first supply switch and said second supply switch.

10. The semiconductor integrated circuit according to claim 1 , wherein said ROM decoder includes:

enhancement type transistors and depletion type transistors configured to be arranged in a matrix,

wherein each row of said matrix includes:

a transistor series circuit configured to be provided with a plurality of pairs, each pair being composed of two transistors, one being an enhancement type transistor and the other being a depletion type transistor that are adjacent to each other,

wherein one end of said transistor series circuit is connected to corresponding one of said plurality of connection points of said ladder resistor, and

the other end of said transistor series circuit is mutually connected to the other ends of the other transistor series circuits in the other rows to be connected to a post-stage circuit,

wherein gates of enhancement type transistors and depletion type transistors included in each column of said matrix are mutually connected, and

said data signal is supplied to gates of odd-numbered columns of said matrix, and an inversion signal of said data signal is supplied to gates of even-numbered columns of said matrix.

11. A method of testing a ROM decoder of a semiconductor integrated circuit, wherein said semiconductor integrated circuit includes:

a ladder resistor configured to include a plurality of resistors series-connected to each other and be supplied with a correction voltage at least one of both ends of said series connection and a plurality of connection points in said series connection to generate a plurality of gradation voltages at said plurality of connection points;

a ROM decoder configured to select one of said plurality of gradation voltages generated by said ladder resistor, based on a supplied data signal; and

a test circuit configured to measure a leakage current in said ROM decoder,

said method comprising:

supplying a data signal to said ROM decoder;

supplying different power source voltages at both ends of said series connection;

separating said series connection at a certain portion based on said data signal; and

measuring a leakage current of said ROM decoder.