Liquid crystal display device and method for fabricating the same
Disclosed are a liquid crystal display device employing an amorphous zinc oxide-based semiconductor as an active layer, and a method for fabricating the same, whereby device stability can be secured by employing an etch stopper structure and device characteristics can be enhanced by minimizing exposure and deterioration of the active layer excluding content regions by virtue of the design of the etching stopper in a shape like “H”. Also, the liquid crystal display device and the fabrication method thereof can further form a semiconductor pattern and an insulating layer pattern on the intersection between the gate line and the data line, so as to compensate a stepped portion, thereby preventing an occurrence of short-circuit.
1. A method for fabricating a liquid crystal display device comprising:
forming a gate electrode and a gate line on an array substrate;
forming a gate insulating layer on the array substrate with the gate electrode and the gate line formed thereon;
forming an active layer on the gate electrode having the gate insulating layer formed thereon, the active layer made of an amorphous zinc oxide-based semiconductor;
forming an etch stopper in a shape like “H” on the active layer, the etch stopper obscuring the active layer excluding a contact region;
forming source and drain electrodes on the active layer, the source and drain electrodes being electrically connected to the contact region of the active layer, and forming a data line defining a pixel region by intersecting with the gate line;
forming a passivation layer on the array substrate having the source and drain electrodes and the data line formed thereon;
forming a contact hole for exposing a part of the drain electrode by removing a partial region of the passivation layer;
forming a pixel electrode, the pixel electrode being electrically connected to the drain electrode via the contact hole; and
attaching the array substrate and a color filter substrate in a facing manner.
2. The method of claim 1 , wherein the etch stopper is made of an insulating layer, the insulating layer comprising silicon oxide and silicon nitride.
3. The method of claim 2 , further comprising forming a semiconductor pattern on the gate line present on the intersection between the gate line and the data line, the semiconductor pattern made of the amorphous zinc oxide-based semiconductor.
4. The method of claim 3 , further comprising forming an insulating layer pattern made of the insulating layer on the semiconductor pattern, the insulating layer pattern obscuring the semiconductor pattern and the gate line.
5. The method of claim 1 , wherein the etch stopper is formed in the shape like “H” by etching upper and lower central portions thereof for connection between the active layer and the source and drain electrodes.
6. The method of claim 1 , wherein the exposed contact region of the active layer experiences a surface treatment or thermal treatment to decrease resistance.
7. The method of claim 1 , wherein the active layer is formed with a-IGZO semiconductor.
8. The method of claim 1 , wherein the amorphous zinc oxide-based semiconductor layer is formed under the conditions that a deposition speed with respect to DC or RF sputtering is in the range of 1 to 200 Å/sec and an oxygen concentration in a reactive gas during sputtering is in the range of 1 to 40%, the conditions depending on process conditions.
9. A liquid crystal display device comprising:
a gate electrode and a gate line formed on an array substrate;
a gate insulating layer formed on the array substrate with the gate electrode and the gate line formed thereon;
an active layer formed on the gate electrode having the gate insulating layer formed thereon, the active layer made of an amorphous zinc oxide-based semiconductor;
an etch stopper formed on the active layer in a shape like “H,” the etch stopper obscuring the active layer excluding a contact region;
a data line formed on the active layer to define a pixel region by intersecting with the source and drain electrodes and the gate line electrically connected to the contact region of the active layer;
a passivation layer formed on the array substrate with the source and drain electrodes and the data line formed thereon;
a contact hole formed by removing a partial region of the passivation layer to expose a part of the drain electrode;
a pixel electrode electrically connected to the drain electrode via the contact hole; and
a color filter substrate attached to the array substrate to face each other.
10. The device of claim 9 , wherein the etch stopper is made of an insulating layer, the insulating layer comprising silicon oxide and silicon nitride.
11. The device of claim 10 , further comprising a semiconductor pattern formed on the gate line present on the intersection between the gate line and the data line, the semiconductor pattern made of the amorphous zinc oxide-based semiconductor.
12. The device of claim 11 , further comprising an insulating layer pattern formed on the semiconductor pattern to obscure the semiconductor pattern and the gate line, the insulating layer pattern made of the insulating layer.
13. The device of claim 9 , wherein the etch stopper is formed in the shape like “H” by etching upper and lower central portions thereof for connection between the active layer and the source and drain electrodes.
14. The device of claim 9 , wherein the active layer has an alignment margin of about 1.5 μm in a longitudinal direction of the gate electrode.
15. The device of claim 9 , wherein the contact region of the active layer overlap with the gate electrode with a width of about 1.5 μm and simultaneously overlap with the source and drain electrodes with a width of about 3 μm.
16. The device of claim 9 , wherein the “H” shaped etch stopper overlaps with the source and drain electrodes with a width of about 1.5 μm at a central portion thereof excluding right and left protruded portions thereof.