IP Library Granted Patent US 8,409,992
Granted Patent B2
US 8,409,992 · App. 12/850,019 · Granted Apr 2, 2013

Method for producing a polished semiconductor wafer

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Quick Facts
Patent No.
US 8,409,992
App. No.
12/850,019
Granted
Apr 2, 2013
Kind
B2
Abstract

A polished semiconductor wafer of high flatness is produced by the following ordered steps: slicing a semiconductor wafer from a rod composed of semiconductor material, material-removal processing of at least one side of the semiconductor wafer, and polishing of at least one side of the semiconductor wafer, wherein the semiconductor wafer has, after the material-removing processing and before the polishing on at least one side to be polished, along its margin, a ring-shaped local elevation having a maximum height of at least 0.1 μm, wherein the local elevation reaches its maximum height within a 10 mm wide ring lying at the edge of the semiconductor wafer.

Claims (17)

1. A method for producing a polished semiconductor wafer having two sides and an edge, comprising the following steps in the stated order:

a) slicing a semiconductor wafer from a rod composed of semiconductor material,

b) material-removal processing at least one side of the semiconductor wafer, and

c) polishing at least one side of the semiconductor wafer,

wherein the semiconductor wafer has along its margin, after material-removal processing and before polishing on at least one side to be polished, a ring-shaped local elevation having a maximum height of at least 0.1 μm, wherein the local elevation reaches its maximum height within a 10 mm wide ring proceeding inwardly from the edge of the semiconductor wafer.

2. The method of claim 1 , wherein material removal caused by polishing, on each side of the semiconductor wafer that is polished, is 3 to 30 μm.

3. The method of claim 1 , wherein the material-removal processing further comprises at least one treatment of the semiconductor wafer with a liquid etchant, wherein the etchant flows during the treatment substantially parallel to the surfaces of the semiconductor wafer onto a margin of the semiconductor wafer, and wherein the local elevation is produced by an at least partial shielding of the ring proceeding inwardly from the edge of the semiconductor wafer against the etchant flowing directly thereon.

4. The method of claim 1 , wherein the material-removal processing comprises at least one treatment of the semiconductor wafer with a liquid etchant, wherein the etchant is sprayed onto at least one side of the semiconductor wafer, wherein the ring proceeding inwardly from the edge of the semiconductor wafer is at least partly covered.

5. The method of claim 1 , wherein the material-removal processing comprises at least one grinding treatment of at least one side of the semiconductor wafer by means of at least one cup grinding disk, wherein the at least one cup grinding disk is positioned relative to the semiconductor wafer during the grinding treatment in such a way that a ring proceeding inwardly from the edge of the semiconductor wafer remains unprocessed, such that the local elevation arises during the grinding treatment on the surface of the ring.

6. The method of claim 1 , wherein the local elevation reaches its maximum height within a 5 mm wide ring proceeding inwardly from the edge of the semiconductor wafer.

7. The method of claim 6 , wherein the maximum height of the local elevation is 0.1 to 10 μm.

8. The method of claim 6 , wherein the maximum height of the local elevation is 0.5 to 5 μm.

9. The method of claim 6 , wherein material removal caused by polishing, on each side of the semiconductor wafer that is polished, is 3 to 30 μm.

10. The method of claim 1 , wherein the maximum height of the local elevation is 0.1 to 10 μm.

11. The method of claim 10 , wherein material removal caused by polishing, on each side of the semiconductor wafer that is polished, is 3 to 30 μm.

12. The method of claim 1 , wherein the maximum height of the local elevation is 0.5 to 5 μm.

13. The method of claim 12 , wherein material removal caused by polishing, on each side of the semiconductor wafer that is polished, is 3 to 30 μm.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2010
From: MOECKEL, BERTRAM; FRANKE, HELMUT
To: SILTRONIC AG
Reel/Frame 024787/0716 →