Systems and methods of smooth light load operation in a DC/DC converter
Systems and devices for smooth light load operation in a DC/DC converter are presented. The disclosed systems and methods enable smooth discontinuous conduction mode (DCM)/continuous conduction mode (CCM) transition. The disclosed systems and methods of smooth light load operation in a DC/DC converter may also avoid the generation of sub-harmonics during light load operation. In an example embodiment, a rising ramp is used to control the ON time of the converter oscillator, while a falling ramp controls the OFF time. During DCM operation, the minimum value of the falling ramp is clamped. The clamping of the falling ramp ensures a substantially similar level of the error amplifier output in both CCM and DCM and avoids disturbances caused by a difference in the error amplifier outputs between the modes.
1. A DC-DC converter, comprising:
a switch; and
a voltage mode controller, the controller comprising:
a rising ramp signal generator;
a falling ramp signal generator;
a falling ramp clamp configured to clamp an output of the falling ramp signal generator;
a first comparator configured to compare a rising ramp signal to an output of an error amplifier (COMP signal) for generating an on time for controlling the switch;
a second comparator configured to compare a falling ramp signal to the COMP signal for generating an off time for controlling the switch; and
an RS flip flop configured to receive outputs of the first comparator and the second comparator to generate a pulse width modulation signal, wherein an output voltage from the error amplifier will be substantially constant during continuous conduction mode and discontinuous conduction mode and wherein an output voltage is proportional to a clamp voltage during discontinuous conduction mode.
2. The DC-DC converter of claim 1 , wherein
the output of the first comparator is electrically connected to the RESET input of the RS flip flop; and
the output of the second comparator is electrically connected to the SET input of the RS flip flop.
3. The DC-DC converter of claim 1 , wherein the rising ramp generator comprises a current source configured to generate a first rising ramp signal.
4. The DC-DC converter of claim 3 , wherein the current source is configurable to adjust the slew rate of the first rising ramp signal to adjust the on-time of the oscillator.
5. The DC-DC converter of claim 1 , wherein the falling ramp generator comprises a current sink configured to generate the falling ramp signal.
6. In a DC-DC converter comprising a high side switch coupled between an input node and a switch node, a low side switch coupled between the switch node and a reference potential, and an inductor coupled between the switch node and an output, a controller comprising:
a voltage mode control comprising:
a rising ramp signal generator for generating a first control signal by comparing a rising ramp signal to an output of an error amplifier in a first comparator;
a falling ramp signal generator for generating a second control signal by comparing a falling ramp signal to the output of the error amplifier in a second comparator;
means for combining the first and the second control signals to generate a pulse width modulated (PWM) signal for controlling a regulator;
a falling ramp clamp configured to clamp an output of the falling ramp signal generator to a fixed value proportional to an output voltage when the converter enters a discontinuous conduction mode, wherein an output voltage from the error amplifier will be substantially constant during continuous conduction mode and discontinuous conduction mode and wherein the output voltage is proportional to a clamp voltage during discontinuous conduction mode.
7. A method of operating a controller for a DC-DC converter comprising:
controlling the DC-DC converter and a voltage mode control comprising:
generating a rising ramp signal for generating a first control signal by comparing the rising ramp signal to an error amplifier output;
generating a falling ramp signal for generating a second control signal by comparing the falling ramp signal to the error amplifier output;
combining the first and the second control signals to generate a pulse width modulated (PWM) signal for controlling a regulator;
clamping the falling ramp signal to a fixed value proportional to an output voltage when the converter enters a discontinuous conduction mode, wherein an output voltage from the error amplifier will be substantially constant during continuous conduction mode and discontinuous conduction mode and wherein the output voltage is proportional to a clamp voltage during discontinuous conduction mode.
8. The power supply control circuit of claim 6 , further comprising a zero crossing comparator configured to determine when the inductor current enters discontinuous conduction mode.
9. The power supply control circuit of claim 6 , wherein the falling ramp signal is clamped to a fixed value.
10. The power supply control circuit of claim 6 , further comprising a current source configured to generate the first rising ramp signal.
11. The power supply control circuit of claim 10 , wherein the current source is configurable to adjust a slew rate of the first rising ramp signal to adjust the on-time of the oscillator.
12. The method of claim 7 , further comprising determining when the converter enters discontinuous conduction mode by monitoring inductor current in the DC/DC converter.
13. The method of claim 12 , wherein the determining step comprises monitoring the inductor current with a zero crossing comparator, the zero crossing comparator outputting a logic level HIGH signal when the inductor current substantially reaches zero, the determining of discontinuous conduction mode having been entered when N consecutive logic level HIGH levels are detected.
14. The method of claim 7 , wherein the falling ramp signal is clamped to a fixed value.
15. The method of claim 7 , wherein the falling ramp signal is clamped to a value substantially proportional to the output.
16. The method of claim 7 , further comprising reducing a slew rate of the first rising ramp signal to increase an on time of the oscillator, generating hysteresis for the clamping.