Semiconductor package and method of manufacturing the same
A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.
1. A semiconductor package comprising:
a substrate having an insulation layer formed with a first surface roughness in a first region and a second surface roughness in a second region;
a semiconductor chip; and
a protection layer between the first region and the semiconductor chip,
wherein top surfaces of the first region and the second region are coplanar.
2. The semiconductor package of claim 1 , wherein the surface roughness of the first region has a depth and a width different than a depth and a width of the second region.
3. The semiconductor package of claim 1 , wherein the second region comprises a plurality of grooves.
4. The semiconductor package of claim 1 , wherein the second region surrounds the first region.
5. The semiconductor package of claim 1 , wherein the surface roughness of the first region has a flowability of the protection layer different from a flowability of the protection layer in the second region.
6. The semiconductor package of claim 5 , wherein the flowability of the protection layer in the first region is greater than the flowability of the protection layer in the second region.
7. The semiconductor package of claim 1 , wherein the first region has a wettability of the protection layer different from a wettability of the protection layer in the second region.
8. The semiconductor package of claim 1 , wherein the protection layer has at least one boundary located at an edge of the first region and the second region.
9. The semiconductor package of claim 1 , wherein the protection layer has at least two external sides having at least one of a U-shape and a curved shape.
10. The semiconductor package of claim 1 , wherein the substrate has a chip mounting area on which the semiconductor chip is mounted that is smaller than the first region of the substrate.
11. The semiconductor package of claim 1 , wherein:
the second region of the substrate comprises a first portion disposed close to the semiconductor chip and a second portion disposed away from the semiconductor chip; and
the protection layer is not located on the second portion of the second region of the substrate.
12. The semiconductor package of claim 11 , wherein
the first portion of the second region of the substrate has a first width in a first direction parallel to an upper surface of the substrate and the second portion of the second region has a second width in the first direction, and the first width is narrower than the second width.
13. The semiconductor package of claim 11 , wherein the substrate comprises a contact pad area in which one or more contact pads are disposed, and the second portion of the second region includes the contact pad area.
14. The semiconductor package of claim 1 , wherein the first region comprises a first portion with a first surface roughness and a second portion with a second surface roughness, and the first surface roughness and the second surface roughness of the first region are different from the surface roughness of the second region.
15. The semiconductor package of claim 14 , wherein the second region comprises a first portion spaced apart from a chip mounting area by a first distance and a second portion spaced apart from a chip mounting area by a second distance.
16. The semiconductor package of claim 14 , wherein the substrate comprises a contact pad area in which one or more contact pad are disposed, and the second portion is spaced apart from the contact pad area by a third distance.
17. The semiconductor package of claim 1 , wherein the first region comprises a plurality of grooves.
18. A semiconductor package, comprising:
a substrate having connection terminals to connect to a semiconductor chip; and
an insulation layer formed on the substrate to have a first region including a first plurality of grooves and a second region including a second plurality of grooves different from the first plurality of grooves and coplanar with the first region,
wherein the first region includes a chip mounting area corresponding to the connection terminals, and
the second region has a surface roughness that is different from a surface roughness of the first region.
19. The semiconductor package according to claim 18 , wherein the second region entirely surrounds the first region.
20. The semiconductor package according to claim 18 , wherein the second region surrounds only three sides of the first region.
21. The semiconductor package according to claim 18 , wherein the first region has a substantially flat surface.
22. The semiconductor package according to claim 18 , wherein the second region has a surface roughness greater than that of the first region.
23. The semiconductor package according to claim 22 , wherein the second region has a center line average surface roughness between 0.01-0.5 μm.
24. The semiconductor package according to claim 18 , further comprising a third region surrounding the second region and having a surface roughness different from the surface roughness of the first region and the second region.
25. The semiconductor package according to claim 24 , wherein the surface roughness of the third region is greater than the surface roughness of the first and second regions.
26. The semiconductor package according to claim 25 , wherein the surface roughness of the second region is greater than the surface roughness of the first region.
27. The semiconductor package according to claim 26 , wherein each of the second and third regions has a surface shape substantially corresponding to a square-wave shape, each of the second and third regions having a plurality of troughs and peaks of different heights, depths, and widths to define the surface roughness of the second and third regions, respectively.
28. The semiconductor package according to claim 24 , further comprising:
the semiconductor chip mounted to the connection terminals of the substrate; and
underfill resin located between the semiconductor chip and the first region of the insulating layer,
wherein the surface roughness of the second region prevents the underfill resin from flowing past the second region.
29. The semiconductor package according to claim 24 , wherein the second region includes a first sub-region and a second sub-region separated by a surface that has substantially the same surface roughness as the surface roughness of the first region.