IP Library Granted Patent US 7,998,818
Granted Patent B2
US 7,998,818 · App. 12/862,799 · Granted Aug 16, 2011

Method for making semiconductor element structure

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Quick Facts
Patent No.
US 7,998,818
App. No.
12/862,799
Granted
Aug 16, 2011
Kind
B2
Abstract

A method for forming a semiconductor element structure is provided. First, a substrate including a first MOS and a second MOS is provided. The gate electrode of the first MOS is connected to the gate electrode of the second MOS, wherein the first MOS includes a first high-K material and a first metal for use in a first gate, and a second MOS includes a second high-K material and a second metal for use in a second gate. Then the first gate and the second gate are partially removed to form a connecting recess. Afterwards, the connecting recess is filled with a conductive material to form a bridge channel for electrically connecting the first metal and the second metal.

Claims (15)

1. A method for forming a semiconductor element structure, comprising:

providing a substrate comprising a first MOS and a second MOS adjacent to said first MOS, wherein said first MOS comprises a first high-K material and a first metal for use in a first gate and said second MOS comprises a second high-K material and a second metal for use in a second gate;

partially removing said first gate and said second gate to form a connecting recess; and

filling said connecting recess with a conductive material to form a bridge channel for electrically connecting said first metal and said second metal, wherein said bridge channel is embedded in at least one of said first metal and said second metal.

2. The method of claim 1 , wherein forming said connecting recess is carried out with the help of a photoresist.

3. The method of claim 1 , wherein forming said connecting recess is carried out by using a wet etching.

4. The method of claim 3 , wherein said wet etching only selectively removes said first high-K material and said second high-K material.

5. The method of claim 3 , wherein said wet etching partially removes said first high-K material, said second high-K material, said first metal and said second metal.

6. The method of claim 3 , wherein said wet etching which comprises multiple stages removes said first high-K material, said second high-K material, said first metal and said second metal.

7. The method of claim 3 , wherein forming said connecting recess is carried out by using a dry etching.

8. The method of claim 7 , wherein said dry etching only selectively removes said first high-K material and said second high-K material.

9. The method of claim 7 , wherein said dry etching partially removes said first high-K material, said second high-K material, said first metal and said second metal.

10. The method of claim 1 , wherein forming said connecting recess is carried out by using energy burning in the absence of a photoresist.

11. The method of claim 1 , wherein forming said bridge channel is carried out by using an electroplating.

12. The method of claim 1 , wherein forming said bridge channel is carried out by an electroless plating.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2010
From: CHIANG, TIAN-FU; CHENG, LI-WEI; HSU, CHE-HUA; YU, CHIH-HAO; CHOU, CHENG-HSIEN; LAI, CHIEN-MING; CHEN, YI-WEN; LIN, CHIEN-TING; MA, GUANG-HWA
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 024882/0164 →