Granted Patent B2

US 8,946,904 · App. 12/869,844 · Granted Feb 3, 2015

Abstract

Claims (55)

1. A semiconductor package, comprising:

a substrate comprising a plurality of layers, a first side and a second side; and a via extending through the substrate from the first side to the second side, the via comprising:

a first substrate via extending through a first layer of the plurality of layers, the first substrate via having a first cross-sectional area;

a first capture pad disposed under the first substrate via, wherein the first capture pad physically contacts the first substrate via on a first side and is adapted to electrically contact a semiconductor die disposed over a top of a second side opposing the first side;

a second substrate via extending through a second layer of the plurality of layers, the second substrate via physically contacting the first capture pad, the second substrate via having a second cross-sectional area that is greater than the first cross-sectional area; and

a second capture pad disposed under the second substrate via, the second capture pad having a second cross-sectional area that is greater than the first cross-sectional area, wherein the second capture pad physically contacts the second substrate via;

a third substrate via extending through a third layer of the plurality of layers, the third substrate via having a third cross-sectional area that is greater than the second cross-sectional area, wherein the third substrate via physically contacts the second capture pad; and

a third capture pad disposed under the third layer, wherein the third capture pad physically contacts the third substrate via.

2. A semiconductor package as claimed in claim 1 , wherein the first capture pad has a first cross-sectional areal dimension and the second capture pad has a second cross-sectional areal dimension, which is greater than the first cross-sectional areal dimension, and the third capture pad has a third cross-sectional areal dimension that is greater than the second cross-sectional area dimension.

3. A semiconductor package as claimed in claim 1 , wherein each of the plurality of layers comprises a dielectric material.

4. A semiconductor package as claimed in claim 1 , wherein each of the plurality of layers comprises a ceramic material.

5. A semiconductor package as claimed in claim 1 , further comprising a contact pad disposed over the first side of the substrate.

6. A semiconductor package as claimed in claim 5 , further comprising a solder bump disposed over the contact pad.

7. A semiconductor package as claimed in claim 6 , wherein the die is disposed over the solder bump.

8. A semiconductor package as claimed in claim 5 , wherein the die is disposed over the contact pad.

9. A substrate, comprising:

a plurality of layers, a first side and a second side; and a via extending through the plurality of layers from the first side to the second side, the via comprising:

a first substrate via extending through a first layer of the plurality of layers, the first substrate via having a first cross-sectional area;

a first capture pad disposed under the first substrate via, wherein the first capture pad physically contacts the first substrate via on a first side and is adapted to electrically contact a semiconductor die disposed over a top of a second side opposing the first side;

a second substrate via extending through a second layer of the plurality of layers, the second substrate via physically contacting the first capture pad, the second substrate via having a second cross-sectional area that is greater than the first cross-sectional area; and

a second capture pad disposed under the second layer, the second capture pad having a second cross-sectional area that is greater than the first cross-sectional area, wherein the second capture pad physically contacts the second substrate via;

a third substrate via extending through a third layer of the plurality of layers, the third substrate via having a third cross-sectional area that is greater than the second cross-sectional area, wherein the third substrate via physically contacts the second capture pad; and

a third capture pad disposed under the third layer, wherein the third capture pad physically contacts the third substrate via.

10. A substrate as claimed in claim 9 , wherein the first capture pad has a first cross-sectional areal dimension and the second capture pad has a second cross-sectional areal dimension, which is greater than the first cross-sectional areal dimension, and the third capture pad has a third cross-sectional areal dimension that is greater than the second cross-sectional area dimension.

11. A substrate as claimed in claim 9 , wherein each of the plurality of layers comprises a dielectric material.

12. A substrate as claimed in claim 9 , wherein each of the plurality of layers comprises a ceramic material.

13. A substrate as claimed in claim 9 , further comprising a contact pad disposed over the first side of the plurality of layers.

14. A semiconductor package, comprising:

a substrate comprising a plurality of layers, a first side and a second side; and a via extending through the substrate from the first side to the second side, the via comprising:

a first substrate via extending through a first layer of the plurality of layers, the first substrate via having a first cross-sectional area;

a first capture pad disposed under the first substrate via, wherein the first capture pad physically contacts the first substrate via;

a second substrate via extending through a second layer of the plurality of layers, the second substrate via physically contacting the first capture pad, the second substrate via having a second cross-sectional area that is greater than the first cross-sectional area; and

a second capture pad disposed under the second substrate via, the second capture pad having a second cross-sectional area that is greater than the first cross-sectional area, wherein the second capture pad physically contacts the second substrate via;

a third substrate via extending through a third layer of the plurality of layers, the third substrate via having a third cross-sectional area that is greater than the second cross-sectional area, wherein the third substrate via physically contacts the second capture pad; and

a third capture pad disposed under the third layer, wherein the third capture pad physically contacts the third substrate via, wherein the first capture pad has a first cross-sectional areal dimension and the second capture pad has a second cross-sectional areal dimension, which is greater than the first cross-sectional areal dimension, and the third capture pad has a third cross-sectional areal dimension that is the same as the second cross-sectional areal dimension.

15. A semiconductor package as claimed in claim 14 , wherein each of the plurality of layers comprises a dielectric material.

16. A semiconductor package as claimed in claim 14 , wherein each of the plurality of layers comprises a ceramic material.

17. A semiconductor package as claimed in claim 14 , further comprising a contact pad disposed over the first side of the substrate.

18. A semiconductor package as claimed in claim 17 , further comprising a solder bump disposed over the contact pad.

19. A semiconductor package as claimed in claim 14 , wherein the semiconductor die is disposed over the contact pad.

20. A semiconductor package as claimed in claim 19 , wherein the semiconductor die is disposed over the solder bump.

21. A substrate, comprising:

a plurality of layers, a first side and a second side; and a via extending through the substrate from the first side to the second side, the via comprising:

a first substrate via extending through a first layer of the plurality of layers, the first substrate via having a first cross-sectional area;

a first capture pad disposed under the first substrate via, wherein the first capture pad physically contacts the first substrate via;

a second substrate via extending through a second layer of the plurality of layers, the second substrate via physically contacting the first capture pad, the second substrate via having a second cross-sectional area that is greater than the first cross-sectional area; and

a second capture pad disposed under the second layer, the second capture pad having a second cross-sectional area that is greater than the first cross-sectional area, wherein the second capture pad physically contacts the second substrate via;

a third substrate via extending through a third layer of the plurality of layers, the third substrate via having a third cross-sectional area that is greater than the second cross-sectional area, wherein the third substrate via physically contacts the second capture pad; and

a third capture pad disposed under the third layer, the third capture pad physically contacting the third substrate via, wherein the first capture pad has a first cross-sectional areal dimension and the second capture pad has a second cross-sectional areal dimension, which is greater than the first cross-sectional areal dimension, and the third capture pad has a third cross-sectional areal dimension that is the same as the second cross-sectional areal dimension.

22. A semiconductor package as claimed in claim 21 , wherein each of the plurality of layers comprises a dielectric material.

23. A semiconductor package as claimed in claim 21 , wherein each of the plurality of layers comprises a ceramic material.

24. A semiconductor package as claimed in claim 21 , further comprising a contact pad disposed over the first side of the plurality of layers.

25. A semiconductor package as claimed in claim 24 , further comprising a solder bump disposed over the contact pad.

26. A semiconductor package as claimed in claim 25 , wherein the semiconductor die is disposed over the solder bump.

27. A semiconductor package as claimed in claim 21 , wherein the semiconductor die is disposed over the contact pad.

Assignments (8)