Semiconductor light emitting device
View Patent ↗According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting portion. The light emitting portion is provided between the semiconductor layers and includes barrier layers and well layers alternately stacked. An n-side end well layer which is closest to the n-type semiconductor layer contains In wn Ga 1-wn N and has a layer thickness t wn . An n-side end barrier layer which is closest to the n-type semiconductor layer contains In bn Ga 1-bn N and has a layer thickness t bn . A p-side end well layer which is closest to the p-type semiconductor layer contains In wp Ga 1-wp N and has a layer thickness t wp . A p-side end barrier layer which is closest to the p-type semiconductor contains In bp Ga 1-bp N and has a layer thickness t bp . A value of (wp×t wp +bp×t bp )/(t wp +t bp ) is higher than (wn×t wn +bn×t bn )/(t wn +t bn ) and is not higher than 5 times (wn×t wn +bn×t bn )/(t wn +t bn ).
1. A semiconductor light emitting device, comprising:
an n-type semiconductor layer containing a nitride semiconductor;
a p-type semiconductor layer containing a nitride semiconductor; and
a light emitting portion provided between the n-type semiconductor layer and the p-type semiconductor layer, the light emitting portion including a plurality of barrier layers and a plurality of well layers, the plurality of barrier layers and the plurality of well layers being alternately stacked,
the well layers including an n-side end well layer which is one of the well layers and is closest to the n-type semiconductor layer among the well layers, the n-side end well layer containing In wn Ga 1-wn N, where In composition ratio wn is an atomic ratio of In among group III elements, the n-side end well layer having a layer thickness t wn (nanometer),
the barrier layers including an n-side end barrier layer which is one of the barrier layers and is closest to the n-type semiconductor layer among the barrier layers, the n-side end barrier layer containing In bn Ga 1-bn N, where In composition ratio bn is an atomic ratio of In among group III elements, the n-side end barrier layer having a layer thickness t bn (nanometer),
the well layers including a p-side end well layer which is another of the well layers and is closest to the p-type semiconductor layer among the well layers, the p-side end well layer containing In wp Ga 1-wp N, where In composition ratio wp is an atomic ratio of In among group III elements, the p-side end well layer having a layer thickness t wp (nanometer),
the barrier layers including a p-side end barrier layer which is another of the barrier layers and is closest to the p-type semiconductor layer among the barrier layers in a region between the p-side end well layer and the n-type semiconductor layer, the p-side end barrier layer containing In bp Ga 1-bp N, where In composition ratio by is an atomic ratio of In among group III elements, the p-side end barrier layer having a layer thickness t bp (nanometer),
a first ratio being defined as (wp×t wp +bp×t bp )/(t wp +t bp ),
a second ratio being defined as (wn×t wn +bn×t bn )/(t wn +t bn ),
the first ratio being higher than 1.9 times the second ratio and being not higher than 2.3 times the second ratio,
wherein the In composition ratio wp is higher than the In composition ratio wn and the thickness t bp is smaller than the thickness t bn .
2. The device according to claim 1 , wherein the layer thickness t wp is larger than the layer thickness t wn .
3. The device according to claim 2 , wherein the In composition ratio wp is not lower than 0.10 and not higher than 0.20.
4. The device according to claim 1 , wherein the In composition ratio by is higher than the In composition ratio bn.
5. The device according to claim 1 , wherein the In composition ratio wp is higher than the In composition ratio wn and the thickness t wp is larger than the thickness t wn .
6. The device according to claim 1 , wherein the In composition ratio wp is higher than the In composition ratio wn and the In composition ratio by is higher than the In composition ratio bn.
7. The device according to claim 1 , wherein
the light emitting portion has N (N is an integer of 2 or more) of the well layers,
a j-th (j is an integer of 2 to (N−1)) well layer counted from the n-type semiconductor layer contains In wj Ga 1-wj N, where In composition ratio wj is an atomic ratio of In among group III elements, and the j-th well layer has a well layer thickness t wj ,
a j-th barrier layer counted from the n-type semiconductor layer contains In bj G 1-bj N, where In composition ratio bj is an atomic ratio of In among group III elements, and the j-th barrier layer has a barrier layer thickness t bj , and
(wj×t wj +bj×t bj )/(t wj +t bj ) is not lower than the second ratio and is not higher than the first ratio.
8. The device according to claim 1 , wherein
a light emitting peak wavelength emitted from the light emitting portion is not shorter than 445 nanometers and not longer than 455 nanometers,
the In composition ratio wp is not lower than 0.10 and not higher than 0.20, and
the thickness t wp is not smaller than 1.0 nanometer and not larger than 5.0 nanometers.
9. The device according to claim 1 , wherein the In composition ratio wp is substantially 0.15 and the thickness t wp is substantially 2.5 nanometers.
10. The device according to claim 1 , wherein
the p-side end well layer has a band gap energy corresponding to a light emitting peak wavelength of light emitted from the light emitting portion, and
the n-side end well layer has a band gap energy corresponding to a wavelength shorter than the light emitting peak wavelength.
11. The device according to claim 1 , wherein the In composition ratio bn is substantially twice the In composition ratio wn.
12. The device according to claim 1 , wherein the thickness t bn is substantially twice the thickness t wn .
13. The device according to claim 1 , wherein the n-type semiconductor layer includes an n-type GaN layer and an n-type layer, the n-type layer being provided between the n-type GaN layer and the light emitting portion and containing one of GaN containing Si and InGaN containing Si.
14. The device according to claim 1 , wherein the p-type semiconductor layer includes a p-type GaN layer, a first p-type guide layer provided between the p-type GaN layer and the light emitting portion, a second p-type guide layer provided between the p-type GaN layer and the first p-type guide layer, and a third p-type guide layer provided between the first p-type guide layer and the second p-type guide layer.
15. The device according to claim 1 , further comprising:
a substrate provided on a side of the n-type semiconductor layer opposite to the p-type semiconductor layer; and
a buffer layer provided between the substrate and the n-type semiconductor layer.
16. The device according to claim 1 , wherein the plurality of barrier layers contain an n-type impurity.
17. The device according to claim 1 , wherein a part of the n-type semiconductor layer, the light emitting portion, and the p-type semiconductor layer are partially removed on a first major surface on a side of the p-type semiconductor layer, and the n-type semiconductor layer is exposed on the first major surface.
18. The device according to claim 17 , further comprising:
an n-side electrode in contact with the exposed n-type semiconductor layer; and
a p-side electrode in contact with the p-type semiconductor layer.
19. The device according to claim 1 , wherein the first ratio is not higher than 2.1 times the second ratio.
20. The device according to claim 1 , wherein the first ratio is not higher than 2.0 times the second ratio.
21. The device according to claim 1 , wherein the In composition ratio wp is not lower than 0.10 and not higher than 0.20.