Emitter-follower type bias circuit

1. An emitter-follower bias circuit supplying a bias voltage to a base of an amplification transistor, the emitter-follower bias circuit comprising:

a depletion mode FET boosting a reference voltage;

an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET; and

first and second resistors having different resistance values, wherein

the reference voltage includes complementary first and second reference voltages,

the depletion mode FET includes a first depletion mode FET boosting the first reference voltage, and a second depletion mode FET boosting the second reference voltage,

the first reference voltage boosted by the first depletion mode FET is input to the emitter-follower circuit via the first resistor, and

the second reference voltage boosted by the second depletion mode FET is input to the emitter-follower circuit via the second resistor.

2. The emitter-follower bias circuit according to claim 1 , further comprising a circuit that internally generates the first and second reference voltages from one reference voltage based on an external voltage.

3. An emitter-follower bias circuit supplying a bias voltage to a base of an amplification transistor, the emitter-follower bias circuit comprising:

a depletion mode FET boosting a reference voltage;

an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET;

first and second resistors having different resistance values; and

first and second switches turning ON/OFF according to an external voltage, wherein

the depletion mode FET includes first and second depletion mode FETs,

the first and second switches control whether to operate the first and second depletion mode FETs, respectively,

the reference voltage boosted by the first depletion mode FET is input to the emitter-follower circuit via the first resistor, and

the reference voltage boosted by the second depletion mode FET is input to the emitter-follower circuit via the second resistor.

4. An emitter-follower bias circuit supplying a bias voltage to a base of an amplification transistor, the emitter-follower bias circuit comprising:

a depletion mode FET boosting a reference voltage;

an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET; and

a switch controlling connection of the depletion mode FET and the emitter-follower circuit in response to an external voltage.

5. An emitter-follower bias circuit supplying a bias voltage to a base of an amplification transistor, the emitter-follower circuit comprising:

a depletion mode FET boosting a reference voltage;

an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET;

a first transistor having a collector connected to a power supply, a base connected to an output terminal of the depletion mode FET, and an emitter; and

a second transistor having a collector connected to the output terminal of the depletion mode FET via a resistor, a base connected to the emitter of the first transistor, and an emitter that is grounded.

6. An emitter-follower bias circuit supplying a bias voltage to a base of an amplification transistor, the emitter-follower bias circuit comprising:

a depletion mode FET boosting a reference voltage;

an emitter-follower circuit generating the bias voltage in response to the reference voltage boosted by the depletion mode FET;

a second depletion mode FET having a gate and a source which are mutually connected, and a drain connected to a power supply;

a first transistor having a collector and a base which are connected to the source of the second depletion mode FET, and an emitter that is grounded; and

a second transistor having a collector connected to an output terminal of the depletion mode FET via a resistor, a base connected to the base of the first transistor, and an emitter that is grounded.