Semiconductor device and method of manufacturing same
View Patent ↗A semiconductor device with high reliability and operation performance is manufactured without increasing the number of manufacture steps. A gate electrode has a laminate structure. A TFT having a low concentration impurity region that overlaps the gate electrode or a TFT having a low concentration impurity region that does not overlap the gate electrode is chosen for a circuit in accordance with the function of the circuit.
1. A semiconductor device comprising:
a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
a semiconductor region; and
a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode,
wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a different width from that of the p-channel thin film transistor,
wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor, and
wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
2. A semiconductor device according to claim 1 , wherein the gate electrode of the p-channel thin film transistor does not have a tapered portion.
3. A semiconductor device according to claim 1 , wherein the gate electrode contains a lamination of tungsten and tantalum nitride.
4. A semiconductor device according to claim 1 , wherein the semiconductor device is one of a liquid crystal display device and an EL display device.
5. A semiconductor device according to claim 1 , wherein the semiconductor device is incorporated into one selected from the group consisting of a computer, a camera, a goggle type display, a projector, a telephone, and an electronic book.
6. A semiconductor device according to claim 1 , wherein the gate insulating layer of the p-channel thin film transistor does not have a tapered portion.
7. A semiconductor device comprising:
a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
a semiconductor region; and
a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode,
wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a larger width from that of the p-channel thin film transistor,
wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor,
wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
8. A semiconductor device according to claim 7 , wherein the gate electrode of the p-channel thin film transistor does not have a tapered portion.
9. A semiconductor device according to claim 7 , wherein the gate electrode contains a lamination of tungsten and tantalum nitride.
10. A semiconductor device according to claim 7 , wherein the semiconductor device is one of a liquid crystal display device and an EL display device.
11. A semiconductor device according to claim 7 , wherein the semiconductor device is incorporated into one selected from the group consisting of a computer, a camera, a goggle type display, a projector, a telephone, and an electronic book.
12. A semiconductor device according to claim 7 , wherein the gate insulating layer of the p-channel thin film transistor does not have a tapered portion.
13. A semiconductor device comprising:
a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
a semiconductor region;
a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode; and
an interlayer insulating film over the gate electrode,
wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a different width from that of the p-channel thin film transistor,
wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor, and
wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
14. A semiconductor device according to claim 13 , wherein the gate electrode of the p-channel thin film transistor does not have a tapered portion.
15. A semiconductor device according to claim 13 , wherein the gate electrode contains a lamination of tungsten and tantalum nitride.
16. A semiconductor device according to claim 13 , wherein the interlayer insulating film is in contact with a top surface and a side surface of the semiconductor region.
17. A semiconductor device according to claim 13 , wherein the semiconductor device is one of a liquid crystal display device and an EL display device.
18. A semiconductor device according to claim 13 , wherein the semiconductor device is incorporated into one selected from the group consisting of a computer, a camera, a goggle type display, a projector, a telephone, and an electronic book.
19. A semiconductor device according to claim 13 , wherein the gate insulating layer of the p-channel thin film transistor does not have a tapered portion.
20. A semiconductor device comprising:
a CMOS circuit, wherein the CMOS circuit contains a n-channel thin film transistor and a p-channel thin film transistor;
each of the n-channel thin film transistor and the p-channel thin film transistor comprising:
a semiconductor region;
a gate electrode over the semiconductor region with a gate insulating layer interposed between the semiconductor region and the gate electrode; and
an interlayer insulating film over the gate electrode,
wherein a bottom surface of the gate electrode of the n-channel thin film transistor has a larger width from that of the p-channel thin film transistor,
wherein a taper angle of the gate electrode of the n-channel thin film transistor is different from that of the p-channel thin film transistor, and
wherein the gate insulating layer of the n-channel thin film transistor has a tapered portion.
21. A semiconductor device according to claim 20 , wherein the gate electrode of the p-channel thin film transistor does not have a tapered portion.
22. A semiconductor device according to claim 20 , wherein the gate electrode contains a lamination of tungsten and tantalum nitride.
23. A semiconductor device according to claim 20 , wherein the interlayer insulating film is in contact with a top surface and a side surface of the semiconductor region.
24. A semiconductor device according to claim 20 , wherein the semiconductor device is one of a liquid crystal display device and an EL display device.
25. A semiconductor device according to claim 20 , wherein the semiconductor device is incorporated into one selected from the group consisting of a computer, a camera, a goggle type display, a projector, a telephone, and an electronic book.
26. A semiconductor device according to claim 20 , wherein the gate insulating layer of the p-channel thin film transistor does not have a tapered portion.