Receiver with feedback continuous-time delta-sigma modulator with current-mode input
View Patent ↗In accordance with some embodiments of the present disclosure, a receiver may include a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal and an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal. The downconverter may be coupled to the ADC without an intervening filter element.
1. A receiver, comprising:
a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal; and
an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal, the ADC having a signal transfer function with a transmission zero at a desired frequency;
the ADC comprising:
a plurality of integrators, each integrator configured to convert a sum of current-mode signals received at its input to a voltage-mode signal indicative of an integral over time of the sum of current-mode signals, the plurality of integrators comprising at least:
a first-stage integrator configured to receive at its input the current-mode baseband signal; and
a final-stage integrator configured to produce at its output a final-stage analog signal;
wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator via a resistor such that the resistor carries a first current-mode signal to the input of the subsequent integrator;
a quantizer configured to convert the final-stage analog signal to the digital output signal;
a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the digital output signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC;
a feedforward path from the output of a first integrator of the plurality of integrators to the input of a second integrator of the plurality of integrators, the feedforward path comprising a capacitor have a capacitance selected to provide the transmission zero in the signal transfer function of the ADC at the desired frequency; and
a delay compensation DAC configured to convert the digital output signal into a third current-mode signal such that the third current-mode signal is carried to the input of the final-stage integrator.
2. A receiver according to claim 1 , wherein the downconverter is coupled to the ADC without an intervening filter element.
3. A receiver according to claim 1 , wherein the delay compensation DAC has a time delay different than that of the particular DAC associated with the final-stage integrator.
4. A receiver according to claim 1 , the ADC further comprising a feedback path from the output of one of the plurality of integrators other than the final-stage integrator to the input of the first-stage integrator.
5. A receiver according to claim 4 , the feedback path comprising a second resistor.
6. A receiver comprising:
a downconverter configured to demodulate a modulated wireless signal to produce a current-mode baseband signal; and
an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into a digital output signal, the ADC having a signal transfer function with a transmission zero at a desired frequency;
wherein the ADC comprises:
a plurality of integrators, each integrator configured to convert a sum of current-mode signals received at its input to a voltage-mode signal indicative of an integral over time of the sum of current-mode signals, the plurality of integrators comprising at least:
a first-stage integrator configured to receive at its input the current-mode baseband signal; and
a final-stage integrator configured to produce at its output a final-stage analog signal;
wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator via a resistor such that the resistor carries a first current-mode signal to the input of the subsequent integrator;
a quantizer configured to convert the final-stage analog signal to the digital output signal;
a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the digital output signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC; and
a feedforward path from the output of a first integrator of the plurality of integrators to the input of a second integrator of the plurality of integrators, the feedforward path comprising a capacitor have a capacitance selected to provide the transmission zero in the signal transfer function of the ADC at the desired frequency.
7. A receiver according to claim 6 , the first integrator comprising the first-stage integrator and the second integrator comprising the final-stage integrator.
8. A receiver according to claim 6 , the capacitor comprising a tunable capacitance.
9. An analog-to-digital converter (ADC) configured to convert a current-mode baseband signal into a digital output signal, the ADC comprising:
a plurality of integrators, each integrator configured to convert a sum of current-mode signals received at its input to a voltage-mode signal indicative of an integral over time of the sum of current-mode signals, the plurality of integrators comprising at least:
a first-stage integrator configured to receive at its input the current-mode baseband signal; and
a final-stage integrator configured to produce at its output a final-stage analog signal;
wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator via a resistor such that the resistor carries
a first current-mode signal to the input of the subsequent integrator;
a quantizer configured to convert the final-stage analog signal to the digital output signal;
a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the digital output signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC;
a feedforward path from the output of a first integrator of the plurality of integrators to the input of a second integrator of the plurality of integrators, the feedforward path comprising a capacitor have a capacitance selected to provide a transmission zero in a signal transfer function of the ADC at a desired frequency; and
a delay compensation DAC configured to convert the digital output signal into a third current-mode signal such that the third current-mode signal is carried to the input of the final-stage integrator.
10. An ADC according to claim 9 , wherein the delay compensation DAC has a time delay different than that of the particular DAC associated with the final-stage integrator.
11. An ADC according to claim 9 , the ADC further comprising a feedback path from the output of one of the plurality of integrators other than the final-stage integrator to the input of the first-stage integrator.
12. An ADC according to claim 11 , the feedback path comprising a second resistor.
13. An analog-to-digital converter (ADC) configured to convert a current-mode baseband signal into a digital output signal, the ADC comprising:
a plurality of integrators, each integrator configured to convert a sum of current-mode signals received at its input to a voltage-mode signal indicative of an integral over time of the sum of current-mode signals, the plurality of integrators comprising at least:
a first-stage integrator configured to receive at its input the current-mode baseband signal; and
a final-stage integrator configured to produce at its output a final-stage analog signal;
wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator via a resistor such that the resistor carries
a first current-mode signal to the input of the subsequent integrator;
a quantizer configured to convert the final-stage analog signal to the digital output signal;
a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the digital output signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC; and
a feedforward path from the output of a first integrator of the plurality of integrators to the input of a second integrator of the plurality of integrators, the feedforward path comprising a capacitor have a capacitance selected to provide a transmission zero in a signal transfer function of the ADC at a desired frequency.
14. An ADC according to claim 13 , the first integrator comprising the first-stage integrator and the second integrator comprising the final-stage integrator.
15. An ADC according to claim 13 , the capacitor comprising a tunable capacitance.
16. An ADC according to claim 13 , further comprising a delay compensation DAC configured to convert the digital output signal into a third current-mode signal such that the third current-mode signal is carried to the input of the final-stage integrator, wherein the delay compensation DAC has a time delay different than that of the particular DAC associated with the final-stage integrator.
17. An ADC according to claim 13 , the ADC further comprising a feedback path from the output of one of the plurality of integrators other than the final-stage integrator to the input of the first-stage integrator.
18. An ADC according to claim 17 , the feedback path comprising a second resistor.
19. A wireless communication element, comprising:
a transmit path configured to convert a first digital signal into a first modulated wireless communication signal and transmit the first modulated wireless communication signal; and
a receive path configured to receive a second modulated wireless communication signal and convert the second modulated wireless communication signal into a second digital signal, the receive path comprising:
a downconverter configured to demodulate the second modulated wireless communication signal to produce a current-mode baseband signal; and
an analog-to-digital converter (ADC) configured to convert the current-mode baseband signal into the second digital signal, the ADC having a signal transfer function with a transmission zero at a desired frequency;
the ADC comprising:
a plurality of integrators, each integrator configured to convert a sum of current-mode signals received at its input to a voltage-mode signal indicative of an integral over time of the sum of current-mode signals, the plurality of integrators comprising at least:
a first-stage integrator configured to receive at its input the current-mode baseband signal; and
a final-stage integrator configured to produce at its output a final-stage analog signal;
wherein the plurality of integrators are arranged in a cascade configuration such that an output of each of the plurality of integrators other than the final-stage integrator is coupled to the input of a subsequent integrator via a resistor such that the resistor carries a first current-mode signal to the input of the subsequent integrator;
a quantizer configured to convert the final-stage analog signal to the second digital signal;
a plurality of digital-to-analog converters (DACs), each particular DAC associated with one of the plurality of integrators and configured to convert the second digital signal into a second current-mode signal such that the second current-mode signal is carried to the input of the integrator associated with the particular DAC; and
a feedforward path from the output of a first integrator of the plurality of integrators to the input of a second integrator of the plurality of integrators, the feedforward path including a gain element, wherein the frequency of the transmission zero depends on the gain element, the gain element comprising a capacitor have a capacitance selected to provide the transmission zero in the signal transfer function of the ADC at the desired frequency.
20. A wireless communication element according to claim 19 , wherein the downconverter is coupled to the ADC without an intervening filter element.
21. A wireless communication element according to claim 19 , wherein:
the capacitor comprises a variable capacitor; and
the frequency of the transmission zero depends on the variable capacitor.