Scan or JTAG controllable capture clock generation
View Patent ↗A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.
1. A method of testing a semiconductor device comprising:
shifting a test pattern into a scan chain;
providing control data to a register coupled to a clock control circuit of the semiconductor device, the control data indicating a specified number of test pulses to supply to the scan chain during a capture cycle; and
supplying, via the clock control circuit, the specified number of test pulses to the scan chain during the capture cycle based on the control data contained in the register.
2. The method of claim 1 , wherein providing the control data to the register comprises shifting the control data in as part of the test pattern.
3. The method of claim 1 , wherein the control data includes data that adjusts the timing of the test pulses relative to one another within the capture cycle.
4. The method of claim 1 , wherein shifting the test pattern into the scan chain comprises shifting the test pattern into the scan chain responsive to initiation of a built-in self-test.
5. The method of claim 4 , wherein the register is a JTAG register.
6. The method of claim 1 , wherein the control data is generated by an automatic test pattern generator.
7. The method of claim 1 , wherein the register is a JTAG register.