Granted Patent B1

US 8,140,778 · App. 12/880,018 · Granted Mar 20, 2012

Assignee: Spansion LLC

Abstract

Claims (58)

1. A data capturing device, comprising:

a data capturing device controller that is arranged to send a burst read command; and

a plurality of data capturing components that is arranged to receive a plurality of serial data signals in response to the burst read command, wherein each of the plurality of data capturing components is arranged to receive a separate corresponding one of the plurality of serial data signals, and wherein each of the data capturing components includes:

a DLL component that is arranged to provide a plurality of clock signals, wherein each of the plurality of clock signals is phase-shifted relative to each other clock signal in the plurality of clock signals;

a data sampling component that is arranged to receive the corresponding serial data signal, wherein the corresponding serial data signal includes a preamble, wherein the preamble includes a training pattern, and wherein the data sampling component is arranged to provide a plurality of sampled data signals by sampling the training pattern with each of the plurality of clock signals;

a comparison component that is arranged to provide a plurality of comparison component output signals by comparing each of the plurality of sampled data signals with an expected training pattern for the corresponding serial data signal of a plurality of expected training patterns; and

a valid clock calculation component that is arranged to receive the plurality of comparison component output signals, to select one of the plurality of clock signals as the valid clock signal for the corresponding serial data signal, and to provide a valid clock signal indicating the selected valid clock signal for the corresponding serial data signal, wherein the valid clock calculation component is arranged to select the valid clock by determining which of the sampled data signals matched the expected training pattern for the serial data signal during the entire training pattern, wherein the start of the training pattern is determined based on detecting a start bit in the preamble, and wherein a middle clock signal of the determined matching clocks signals is selected as the valid clock signal,

wherein the data capturing device controller is further configured to, for each of the plurality of data sampling circuits, lock the DLL component of the data sampling circuit to the valid clock signal for the corresponding serial data signal responsive to receiving the valid clock signal for the corresponding serial data signal.

2. The data capturing device of claim 1 , wherein

each of the comparison components includes a plurality of comparators, wherein each of the comparators is arranged to compare the expected training pattern with a separate one of the plurality of sampled data signals, and to provide a comparator output signal in response to the comparison, wherein the comparison component output signal includes the comparator output signal of each of the plurality of comparators.

3. The data capturing device of claim 1 , wherein

the valid clock calculation circuit includes a low-to-high priority encoder and a high-to-low priority encoder.

4. The data capturing device of claim 1 , wherein for each of the plurality of data capturing components:

the DLL component includes means for clock signal generation; or

the data sampling component includes means for data sampling; or

the comparison components includes means for comparing; or

the valid clock calculation component includes means for valid clock calculation.

5. The data capturing device of claim 1 , wherein

each expected training pattern in the plurality of expected training patterns includes a zero to one transition, a one to zero transition, a zero to zero transition, and a one to one transition;

each expected training pattern in the plurality of expected training patterns includes a zero to one transition in which each adjacent bit lane has a one to zero transition in that location; and

each expected training pattern in the plurality of expected training patterns includes a one to zero transition in which adjacent bit lane has a zero to one transition in that location.

6. The data capturing device of claim 5 , wherein

the plurality of expected patterns includes four expected training patterns, one for each of four separate bit lanes.

7. The data capturing device of claim 1 , wherein

each of the data sampling components includes a first stage that includes plurality of flip-flops, wherein each of the plurality of flip-flops has a clock input, each of the plurality of flip-flops is arranged to receive the serial data signal, and wherein each of the plurality of flip flops is arranged to receive a separate one of the plurality of clocks signals at the clock input of the flip flop.

8. The data capturing device of claim 7 , wherein

each of the data sampling components further includes a second stage, wherein the second stage includes another plurality of flip-flops.

9. A method for data capturing, comprising:

sending a burst read command;

receiving a plurality of serial data signals in response to the burst read command, and for each of the plurality of serial data signals:

providing a plurality of clock signals, wherein each of the plurality of clock signals is phase-shifted relative to each other clock signal in the plurality of clock signals, wherein the corresponding serial data signal includes a preamble, wherein the preamble includes a training pattern;

providing a plurality of sampled data signals by sampling the training pattern with each of the plurality of clock signals;

comparing each of the plurality of sampled data signals with an expected training pattern for the corresponding serial data signal of a plurality of expected training patterns;

selecting one of the plurality of clock signals as the valid clock signal for the corresponding serial data signal, including:

determining which of the sampled data signals matched the expected training pattern for the serial data signal during the entire training pattern, wherein the start of the training pattern is determined based on detecting a start bit in the preamble; and

selecting a middle clock signal of the determined matching clock signals of the of clock signals as the valid clock signal; and

locking to the valid clock selected valid clock.

10. The method of claim 9 , wherein

each expected training pattern in the plurality of expected training patterns includes a zero to one transition, a one to zero transition, a zero to zero transition, and a one to one transition;

each expected training pattern in the plurality of expected training patterns includes a zero to one transition in which each adjacent bit lane has a one to zero transition in that location; and

each expected training pattern in the plurality of expected training patterns includes a one to zero transition in which adjacent bit lane has a zero to one transition in that location.

11. The method of claim 10 , wherein

the plurality of expected patterns includes four expected training patterns, one for each of four separate bit lanes.

12. A system, including:

a data capturing device controller that is arranged to send a burst read command; and

a plurality of data capturing components that is arranged to receives a plurality of serial data signals in response to the burst read command, wherein each of the plurality of data capturing components is arranged to receive a separate corresponding one of the plurality of serial data signals, and wherein each of the data capturing components includes:

a DLL component that is arranged to provide a plurality of clock signals, wherein each of the plurality of clock signals is phase-shifted relative to each other clock signal in the plurality of clock signals;

a data sampling component that is arranged to receive the corresponding serial data signal, wherein the corresponding serial data signal includes a preamble, wherein the preamble includes a training pattern, and wherein the data sampling component is arranged to provide a plurality of sampled data signals by sampling the training pattern with each of the plurality of clock signals;

a comparison component that is arranged to provide a plurality of comparison component output signals by comparing each of the plurality of sampled data signals with an expected training pattern for the corresponding serial data signal of a plurality of expected training patterns; and

a valid clock calculation component that is arranged to receive the plurality of comparison component output signals, to select one of the plurality of clock signals as the valid clock signal for the corresponding serial data signal, and to provide a valid clock signal indicating the selected valid clock signal for the corresponding serial data signal, wherein the valid clock calculation component is arranged to select the valid clock by determining which of the sampled data signals matched the expected training pattern for the serial data signal during the entire training pattern, wherein the start of the training pattern is determined based on detecting a start bit in the preamble, and wherein a middle clock signal of the determined matching clocks signals is selected as the valid clock signal,

wherein the data capturing device controller is further configured to, for each of the plurality of data sampling circuits, lock the DLL circuit of the data sampling circuit to the valid clock signal for the corresponding serial data signal responsive to receiving the valid clock signal for the corresponding serial data signal; and

a memory controller that is configured to provide the response to the burst read command such that the burst read commands includes the preamble, and the preamble includes the training pattern.

13. The system of claim 12 , wherein

each expected training pattern in the plurality of expected training patterns includes a zero to one transition, a one to zero transition, a zero to zero transition, and a one to one transition;

each expected training pattern in the plurality of expected training patterns includes a zero to one transition in which each adjacent bit lane has a one to zero transition in that location; and

each expected training pattern in the plurality of expected training patterns includes a one to zero transition in which adjacent bit lane has a zero to one transition in that location.

14. The system of claim 13 , wherein

the plurality of expected patterns includes four expected training patterns, one for each of four separate bit lanes.

Assignments (8)