Apparatus of low power, area efficient FinFET circuits and method for implementing the same
View Patent ↗A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.
1. A FinFET majority gate comprising:
at least three inputs;
an output;
a pull-up network having at least three P-FinFETs connected in series, each of the at least three P-FinFETs has a front gate and a back gate independently coupled to one of the at least three inputs or one of the complements of the at least three inputs, the pull-up network coupled to the output through one of the at least three P-FinFETs; and
a pull-down network having at least three N-FinFETs connected in series, each of the at least three N-FinFETs has a front gate and a back gate independently coupled to one of the at least three inputs or one of the complements of the at least three inputs, the pull-down network coupled to the output through one of the at least three N-FinFETs.
2. The FinFET majority gate of claim 1 , wherein the pull-up network has a first P-FinFET, a second P-FinFET, and a third P-FinFET, each of the first P-FinFET, the second P-FinFET, and the third P-FinFET has a source, a drain, a front gate, and a back gate.
3. The FinFET majority gate of claim 2 , wherein the drain of the first P-FinFET coupled to the output of the majority gate, the drain of the second P-FinFET coupled to the source of the first P-FinFET, the drain of the third P-FinFET coupled to the source of the second P-FinFET.
4. The FinFET majority gate of claim 3 , wherein the source of the third P-FinFET coupled to a high reference voltage.
5. The FinFET majority gate of claim 2 , wherein the first P-FinFET, the second P-FinFET, and the third P-FinFET have input pairs (A′, B′), (A′, C′) and (B′, C′) in no particular order, where A′, B′, C′ are complement of the primary inputs A, B, C of the majority gate.
6. The FinFET majority gate of claim 1 , wherein the pull-down network has a first N-FinFET, a second N-FinFET, and a third N-FinFET, each of the first N-FinFET, the second N-FinFET, and the third N-FinFET has a source, a drain, a front gate, and a back gate.
7. The FinFET majority gate of claim 6 , wherein the drain of the first N-FinFET coupled to the output of the majority gate, the drain of the second N-FinFET coupled to the source of the first N-FinFET, the drain of the third N-FinFET coupled to the source of the second N-FinFET.
8. The FinFET majority gate of claim 7 , wherein the source of the third N-FinFET coupled to a low reference voltage.
9. The FinFET majority gate of claim 6 , wherein the first N-FinFET, the second N-FinFET, and the third N-FinFET have input pairs (A′, B′), (A′, C′) and (B′, C′) in no particular order, where A′, B′, C′ are complement of the primary inputs A, B, C of the majority gate.
10. A FinFET MUX comprising:
at least two data inputs;
a selection input;
an output;
a pull-up network having at least two P-FinFETs connected in series, each of the at least two P-FinFETs has a front gate and a back gate independently coupled to the selection input, the complement of the selection input, one of the at least two data inputs, or one of the complements of the at least two data inputs, the pull-up network coupled to the output through one of the at least two P-FinFETs; and
a pull-down network having at least two N-FinFETs connected in series, each of the at least two N-FinFETs has a front gate and a back gate independently coupled to the selection input, the complement of the selection input, one of the at least two data inputs, or one of the complements of the at least two data inputs, the pull-down network coupled to the output through one of the at least two N-FinFETs.
11. The FinFET MUX of claim 10 , wherein the pull-up network has a first P-FinFET and a second P-FinFET, each of the first P-FinFET and the second P-FinFET has a source, a drain, a front gate, and a back gate.
12. The FinFET MUX of claim 11 , wherein the drain of the first P-FinFET coupled to the output of the MUX, the drain of the second P-FinFET coupled to the source of the first P-FinFET.
13. The FinFET MUX of claim 12 , wherein the source of the second P-FinFET coupled to a high reference voltage.
14. The FinFET MUX of claim 11 , wherein the first P-FinFET and the second P-FinFET have input pairs (S, B′) and (S′, A′), in no particular order, where A′ and B′ are complement of the data inputs A, B, wherein S is the selection input and S′ is the complement of S.
15. The FinFET MUX of claim 10 , wherein the pull-down network has a first N-FinFET and a second N-FinFET, each of the first N-FinFET and the second N-FinFET has a source, a drain, a front gate, and a back gate.
16. The FinFET MUX of claim 15 , wherein the drain of the first N-FinFET coupled to the output of the MUX, the drain of the second N-FinFET coupled to the source of the first N-FinFET.
17. The FinFET MUX of claim 16 , wherein the source of the second N-FinFET coupled to a low reference voltage.
18. The FinFET MUX of claim 15 , wherein the first N-FinFET and the second N-FinFET have input pairs (S, A′) and (S′, B′), in no particular order, where A′ and B′ are complement of the data inputs A, B, wherein S is the selection input and S′ is the complement of S.
19. A computer readable storage medium for generating a digital circuit comprising an output, the computer readable storage medium carrying one or more sequences of one or more instructions which, when executed by one or more processors, cause the one or more processors to perform the computer-implemented steps of:
constructing a logic expression in OR-AND form corresponding to the output of the digital circuit;
constructing a logic expression in OR-AND form corresponding to the complement of the output of the digital circuit;
mapping the logic expressions into a CMOS circuit;
merging two parallel NMOS transistors of the CMOS circuit into a N-FinFET; and
merging two parallel PMOS transistors of the CMOS circuit into a P-FinFET.
20. The computer readable storage medium recited in claim 19 , wherein the one or more sequences of one or more instructions further cause the one or more processors to perform the computer-implemented steps of:
replacing an unpaired NMOS transistor with a N-FinFET; and
replacing an unpaired PMOS transistor with a P-FinFET.