Light emitting diode having vertical topology and method of making the same

1. A method of making a light emitting diode (LED) having vertical topology, comprising:

forming a semiconductor layer on a substrate, the semiconductor layer comprising a first-type layer, an active layer on the first-type layer, and a second-type layer on the active layer;

forming a first electrode on the semiconductor layer, the first electrode comprising an electrical contact and a reflective electrode on the electrical contact;

forming a connection metal layer on the first electrode, the connection metal layer comprising a first metal layer on the first electrode, a diffusion barrier layer on the first metal layer, and a second metal layer on the diffusion barrier layer;

forming a supporting layer on the connection metal layer;

separating the substrate from the semiconductor layer; and

forming a second electrode on a surface of the semiconductor layer exposed by the separation of the substrate.

2. The method according to claim 1 , further comprising etching a chip separation region of the semiconductor layer to form a trench.

3. The method according to claim 1 , wherein the first electrode comprises at least one of Ni, W, Ti, Pt, Au, Pd, Cu, Al, Cr, and Ag.

4. The method according to claim 1 , wherein separating the substrate from the semiconductor layer comprises:

irradiating the portion between the substrate and the semiconductor layer with a laser beam;

generating plasma by melting the semiconductor layer at the portion, due to the irradiation of the laser beam; and

generating the acoustic stress wave by an expansion of the generated plasma.

5. The method according to claim 2 , further comprising forming a passivation layer in the trench.

6. The method according to claim 5 , wherein the passivation layer comprises at least one of SiO 2 , SiN, epoxy-based photoresist, acrylic-based photoresist, SOG, and polyimide.

7. The method according to claim 5 , wherein the passivation layer is partially disposed in the trench.

8. The method according to claim 5 , wherein the passivation layer comprises:

a first passivation layer; and

a second passivation layer on the first passivation layer.

9. The method according to claim 5 , wherein the passivation layer comprises an inorganic layer and/or an organic layer.

10. The method according to claim 2 , wherein etching the chip separation region is performed before forming the first electrode.

11. The method according to claim 1 , wherein the supporting layer has a thickness of 50 to 150 μm.

12. The method according to claim 1 , wherein the supporting layer comprises a wafer or a metal.

13. The method according to claim 1 , wherein separating the substrate from the semiconductor layer comprises irradiating a laser beam to the semiconductor layer through the substrate.

14. The method according to claim 13 , wherein the laser beam has an energy density of more than 0.50 J/cm 2 .

15. The method according to claim 13 , wherein the laser beam has an energy density of 0.60 to 0.75 J/cm 2 .

16. The method according to claim 1 , further comprising forming a light extraction structure on the surface of the semiconductor layer.

17. The method according to claim 16 , wherein forming the light extraction structure comprises forming irregularities into the semiconductor layer.

18. The method according to claim 16 , wherein forming the light extraction structure comprises treating the surface of the semiconductor layer.

19. The method according to claim 18 , wherein treating the surface comprises etching the surface of the semiconductor layer layer.

20. The method according to claim 1 , further comprising dicing out into individual chips.

21. The method according to claim 20 , wherein dicing out into individual chips comprises performing laser-scribing.

22. The method according to claim 1 , wherein at least one of the first metal layer and the second metal layer comprises a bonding layer for attaching the supporting layer.

23. The method according to claim 1 , wherein the first metal layer comprises at least one of Ni, W, Ti, Pt, Au, Pd, Cu, Al, Cr, and Ag.

24. The method according to claim 1 , wherein the diffusion barrier layer comprises at least one of Ni, W, Ti and Pt.

25. The method according to claim 1 , wherein the second metal layer comprises at least one of Au and Cu.

26. The method according to claim 1 , wherein the semiconductor layer further comprises a current diffusion layer on the second-type layer.

27. The method according to claim 26 , wherein the current diffusion layer comprises an InGaN layer or an InGaN/GaN superlattice layer.

28. The method according to claim 1 , wherein a thickness of the reflective electrode is more than 100 Å.

29. The method according to claim 1 , wherein a thickness of the reflective electrode is equal to or less than 5000 Å.

30. The method according to claim 1 , wherein the first-type is n-type and the second-type is p-type.

31. The method according to claim 1 , wherein a thickness of the reflective electrode is more than 1000 Å and less than 5000 Å.

32. The method according to claim 16 , wherein the light extraction structure comprises a photonic crystal structure having a plurality of holes.

33. The method according to claim 32 , wherein the photonic crystal pattern has a period of 0.2 to 2 μm.

34. The method according to claim 16 , wherein a depth of the light extraction structure is in the range of 0.1 μm to the thickness of the first-type layer.

35. The method according to claim 1 , wherein separating the substrate from the semiconductor layer is performed by generating an acoustic stress wave at a portion between the substrate and the semiconductor layer.

36. The method according to claim 35 , wherein the acoustic stress wave is generated by an expansion of plasma confined at the portion between the substrate and the semiconductor layer.