Semiconductor nanowire memory device
According to an embodiment, a semiconductor memory device capable of stably operating even when an element is shrunk is provided. The semiconductor memory device of the embodiment includes: first and second diodes serially connected between power sources of two different potentials, formed by nanowires, and exhibiting negative differential resistances; and a select transistor connected between the first diode and the second diode. The nanowires are preferably silicon nanowires. The thickness of the silicon nanowires is preferably 8 nm or less.
1. A semiconductor memory device comprising:
first and second diodes serially connected between power sources of two different potentials, the diodes being formed by non-doped silicon nanowires or non-doped germanium nanowires, the diodes having a thickness of 10 nm or less, and exhibiting negative differential resistances; and
a select transistor connected between the first diode and the second diode.
2. The device according to claim 1 , wherein the nanowires are silicon nanowires.
3. The device according to claim 2 , wherein a thickness of the silicon nanowires is 8 nm or less.
4. The device according to claim 2 , wherein the silicon nanowires are formed in an SOI layer of an SOI substrate.
5. A semiconductor memory device comprising:
first and second diodes serially connected between power sources of two different potentials, the diodes being formed by non-doped silicon nanowires or non-doped germanium nanowires, the diodes having a thickness of 10 nm or less, and exhibiting negative differential resistances;
a select transistor, a drain electrode of the select transistor being connected between the first diode and the second diode;
a data line being connected to a source electrode of the select transistor; and
an address line being connected to a gate electrode of the select transistor.
6. The device according to claim 5 , wherein the nanowires are silicon nanowires.
7. The device according to claim 6 , wherein a thickness of the silicon nanowires is 8 nm or less.
8. The device according to claim 6 , wherein the silicon nanowires are formed in an SOI layer of an SOI substrate.