IP Library Granted Patent US 8,581,377
Granted Patent B2
US 8,581,377 · App. 12/883,556 · Granted Nov 12, 2013

TSOP with impedance control

Inventors: Belgacem Haba (Saratoga, CA); Brian Marcucci (Phoenix, AZ)
Assignee: Tessera, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,581,377
App. No.
12/883,556
Granted
Nov 12, 2013
Kind
B2
Abstract

A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

Claims (36)

1. A semiconductor device comprising:

a die;

a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die;

at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the lead frame such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path; and

an encapsulant which encapsulates the leads and the conductive element, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the controlled-impedance conduction path has a length of at least one millimeter.

2. A semiconductor device comprising:

a die;

a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die;

at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the lead frame such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path; and

an encapsulant which encapsulates the leads and the conductive element, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the substantial portion of one conductive element has a length of at least 25% of the total length of the conductive element.

3. A semiconductor device comprising:

a die;

a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die;

at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the lead frame such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path; and

an encapsulant which encapsulates the leads and the conductive element, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the die has a front surface and a distance between the plane of the conductive element and the lead plane is equal to or smaller than a distance between the plane of the conductive element and the front surface of the die.

4. A semiconductor device comprising:

a die;

a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die;

at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the lead frame such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path; and

an encapsulant which encapsulates the leads and the conductive element, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the die has a front surface and a distance between the plane of the conductive element and the lead plane is equal to or smaller than a distance between the lead plane and the front surface of the die.

5. A semiconductor device comprising:

a die;

a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die;

at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the lead frame such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path; and

an encapsulant which encapsulates the leads and the conductive element, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the device comprises a top, a bottom, and multiple sides, and wherein the connection regions of the leads extend from one side of the device and the connection region of the conductive element is positioned at the bottom of the device.

6. A semiconductor device comprising:

a die;

a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die;

at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the lead frame such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path; and

an encapsulant which encapsulates the leads and the conductive element, the device including connection regions which are not covered by the encapsulant and which are electrically connected to the leads and the conductive element, at least some of the connection regions being formed integrally with the leads,

wherein the encapsulant defines multiple sides, and wherein the connection regions of the leads extend from one side of the device and the connection region of the conductive element extends from another side of the device.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2011
From: TESSERA RESEARCH LLC
To: TESSERA, INC.
Reel/Frame 026916/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2010
From: HABA, BELGACEM; MARCUCCI, BRIAN
To: TESSERA RESEARCH LLC
Reel/Frame 025594/0382 →
Continuity (1)
Related Publication 20120068317A1 · Mar 22, 2012