Staged via formation from both sides of chip
A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
1. A method of fabricating a semiconductor assembly, comprising:
providing a semiconductor element having a front surface, a rear surface remote from the front surface, and a plurality of conductive pads, each pad having a top surface exposed at the front surface and having a bottom surface remote from the top surface;
forming a hole extending at least through a respective one of the conductive pads by processing applied to the respective one of the conductive pads from above the front surface;
forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the hole and the opening meet at a location between the front and rear surfaces;
forming a first continuous dielectric layer overlying an interior surface of the semiconductor element within the opening;
forming a second continuous dielectric layer partially overlying the respective conductive pad at least at a location above the respective conductive pad and overlying an interior surface of the semiconductor element within the hole; and
forming a conductive interconnect exposed at the rear surface for electrical connection to an external device, the conductive interconnect extending at least into the opening; and
forming a conductive via exposed at the front surface, the conductive via extending at least within the hole and being electrically connected with and directly coupled to the conductive interconnect and the respective conductive pad,
wherein the step of forming the conductive interconnect is performed before the step of forming the conductive via, such that the conductive via is formed in contact with a surface of the conductive interconnect exposed within the hole, and
wherein the step of forming the hole includes:
exposing a surface of the first continuous dielectric layer within the hole; and
extending the hole through the surface of the first continuous dielectric layer to expose the surface of the conductive interconnect within the hole.
2. A method as claimed in claim 1 , wherein the step of forming the conductive interconnect forms a conductive contact coupled to the conductive interconnect, the conductive contact being exposed at the rear surface.
3. A method as claimed in claim 2 , wherein the conductive contact overlies the rear surface of the semiconductor element.
4. A method as claimed in claim 2 , wherein the opening has a first width in a lateral direction along the rear surface, and the conductive contact has a second width in the lateral direction, the first width being greater than the second width.
5. A method as claimed in claim 2 , wherein the conductive contact is aligned in a vertical direction with a portion of the semiconductor element within the opening, the vertical direction being a direction of the thickness of the semiconductor element.
6. A method as claimed in claim 1 , wherein the step of forming the hole is performed such that the hole extends partially through the thickness of the semiconductor element.
7. A method as claimed in claim 6 , wherein the step of forming the hole is performed such that the hole extends up to one-third of the distance between the front surface and the rear surface through the thickness of the semiconductor element, and the opening extends through a remainder of the thickness of the semiconductor element that is not occupied by the hole.
8. A method as claimed in claim 1 , wherein the semiconductor element includes a plurality of active semiconductor devices and at least one of the plurality of conductive pads is electrically connected with at least one of the plurality of active semiconductor devices.
9. A method as claimed in claim 1 , wherein one or more of the hole and the opening are formed by directing a jet of fine abrasive particles towards the semiconductor element.
10. A method as claimed in claim 1 , wherein the step of forming the hole forms two or more holes, and the step of forming the opening is performed such that the opening extends from the rear surface of the semiconductor element to two or more of the holes.
11. A method as claimed in claim 10 , wherein the step of forming the opening is performed such that the opening has a channel shape having a length extending in a first direction along a surface of the semiconductor element, and a width extending a second lateral direction transverse to said first direction, the length being greater than the width.
12. A method as claimed in claim 1 , wherein the processing applied to the respective conductive pad from above the front surface is chemical etching, laser drilling, or plasma etching.
13. A method of fabricating a stacked assembly including at least first and second semiconductor assemblies, each semiconductor assembly being fabricated as claimed in claim 1 , further comprising the step of electrically connecting the first semiconductor assembly with the second semiconductor assembly.
14. A method as claimed in claim 1 , wherein the conductive interconnect is formed by plating a metal layer overlying at least an inner surface of the opening, the conductive interconnect conforming to a contour of the opening.
15. A method as claimed in claim 14 , wherein the conductive interconnect extends along a portion of the inner surface of the opening.
16. A method as claimed in claim 15 , wherein the step of forming the conductive interconnect is performed so as to form two or more conductive interconnects at least within the opening, each of the two or more conductive interconnects extending to a single one of the conductive pads.
17. A method as claimed in claim 14 , wherein the conductive interconnect defines an internal space.
18. A method as claimed in claim 17 , further comprising the step of filling the internal space with a dielectric material.
19. A method as claimed in claim 14 , wherein the conductive interconnect fills a volume between surfaces of the first continuous dielectric layer.
20. A method as claimed in claim 1 , wherein the conductive via is formed by plating a metal layer overlying at least an inner surface of the hole, the conductive via conforming to a contour of the hole.
21. A method as claimed in claim 20 , wherein the conductive interconnect defines an internal space.
22. A method as claimed in claim 21 , further comprising the step of filling the internal space with a dielectric material.
23. A method as claimed in claim 20 , wherein of the conductive via fills a volume between surfaces of the second continuous dielectric layer.
24. A method as claimed in claim 1 , wherein the second continuous dielectric layer partially overlies the top surface of the respective conductive pad, and the step of forming the conductive via forms the conductive via in contact with the top surface of the respective conductive pad and overlying the continuous dielectric layer over the top surface of the respective conductive pad and within the hole.
25. A method of fabricating a semiconductor assembly, comprising:
providing a semiconductor element having a front surface, a rear surface remote from the front surface, and a plurality of conductive pads, each pad having a top surface exposed at the front surface and having a bottom surface remote from the top surface;
forming a hole extending at least through a respective one of the conductive pads by processing applied to the respective one of the conductive pads from above the front surface;
forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the hole and the opening meet at a location between the front and rear surfaces;
forming a continuous dielectric layer partially overlying the respective conductive pad at least at a location above the respective conductive pad and overlying an interior surface of the semiconductor element within the hole; and
forming a conductive interconnect exposed at the rear surface for electrical connection to an external device, the conductive interconnect extending at least into the opening; and
forming a conductive via exposed at the front surface, the conductive via extending at least within the hole and being electrically connected with and directly coupled to the conductive interconnect and the respective conductive pad,
wherein the step of forming the conductive via is performed before the step of forming the conductive interconnect, such that the conductive interconnect is formed in contact with a surface of the conductive via exposed within the opening, and
wherein the step of forming the opening includes:
exposing a surface of the continuous dielectric layer within the opening; and
extending the opening through the surface of the continuous dielectric layer to expose the surface of the conductive via within the opening.