Non-volatile semiconductor storage device with concurrent read operation
View Patent ↗A semiconductor storage device includes a memory cell array including memory cells arranged at respective intersections between first wirings and second wirings. Each of the memory cells includes a rectifier element and a variable resistance element connected in series. A control circuit is configured to apply a first voltage to a selected first wiring and a second voltage lower than the first voltage to a selected second wiring so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring. The control circuit performs a concurrent read operation to perform a read operation from plural memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently. It is possible to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.
1. A method of reading a semiconductor storage device comprising memory cells arranged at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells including a rectifier element and a variable resistance element connected in series, the method comprising:
performing a first concurrent read operation on M of the first wirings (where M is a natural number); and
performing a second concurrent read operation on N of the first wirings (where N<M, N is a natural number) according to a result of a determination of the first concurrent read operation.
2. The method of reading according to claim 1 , wherein
N is a number equal to one half of M, and
the second concurrent read operation involves two read operations to be performed separately in time.
3. The method of reading according to claim 1 , wherein
error correction is performed on read data in the first concurrent read operation, and execution of the second concurrent read operation is begun according to a result of the error correction.
4. The method of reading according to claim 3 , wherein
N is a number equal to one half of M, and
the second concurrent read operation involves two read operations to be performed separately in time.
5. The method of reading according to claim 1 , wherein
a smaller number of the first wirings are applied with a voltage concurrently when a concurrent read operation is performed with respect to initial setting data, as compared with when normal data is read with the concurrent read operation.
6. The method of reading according to claim 5 , wherein
the initial setting data includes first data and second data, the second data representing the complementary data of the first data, and
a determination is made as to whether the initial setting data is read correctly or incorrectly based on a logical operation between the first data and the second data.
7. A semiconductor storage device comprising:
a memory cell array including memory cells arranged at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells including a rectifier element and a variable resistance element connected in series; and
a control circuit configured to apply a first voltage to a selected one of the first wirings and a second voltage lower than the first voltage to a selected one of the second wirings so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring, and
the control circuit being configured to be able to perform a concurrent read operation to perform a read operation from a plurality of the memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently, and being configured to be able to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation, wherein
the control circuit is configured to be able to perform a first concurrent read operation on M of the first wirings (where M is a natural number), then determine whether a result of the read operation is correct or not, and perform a second concurrent read operation on N of the first wirings (where N<M, N is a natural number) according to a result of the.
8. The semiconductor storage device according to claim 7 , wherein
the control circuit is configured to apply the first voltage concurrently to a smaller number of the first wirings when performing the concurrent read operation with respect to initial setting data, as compared with when reading normal data with the concurrent read operation.
9. The semiconductor storage device according to claim 8 , wherein
the initial setting data includes first data and second data, the second data representing the complementary data of the first data, and
the control circuit is configured to determine whether the initial setting data is read correctly or incorrectly based on a logical operation between the first data and the second data.
10. The semiconductor storage device according to claim 7 , wherein
N is a number equal to one half of M, and
the second concurrent read operation involves two read operations to be performed separately in time.
11. The semiconductor storage device according to claim 7 , wherein
the control circuit is configured to perform error correction on read data in the first concurrent read operation, and begin to execute the second concurrent read operation according to a result of the error correction.
12. The semiconductor storage device according to claim 11 , wherein
N is a number equal to one half of M, and
the second concurrent read operation involves two read operations to be performed separately in time.
13. The semiconductor storage device according to claim 7 , wherein
the control circuit is configured to apply the first voltage concurrently to a smaller number of the first wirings when performing the concurrent read operation with respect to initial setting data, as compared with when reading normal data with the concurrent read operation.
14. The semiconductor storage device according to claim 13 , wherein
the initial setting data includes first data and second data, the second data representing the complementary data of the first data, and
the control circuit is configured to determine whether the initial setting data is read correctly or incorrectly based on a logical operation between the first data and the second data.
15. The semiconductor storage device according to claim 13 , wherein
multiple bits of data that are read by a unit of read in the concurrent read operation include the same data.
16. The semiconductor storage device according to claim 15 , wherein
N is a number equal to one half of M, and
the second concurrent read operation involves two read operations to be performed separately in time.
17. The semiconductor storage device according to claim 15 , wherein
the control circuit is configured to perform error correction on read data in the first concurrent read operation, and begin to perform the second concurrent read operation according to a result of the error correction.
18. The semiconductor storage device according to claim 1 , wherein
the second concurrent read operation involves a first read operation and a second read operation initiated before completion of the first read operation.
19. The semiconductor storage device according to claim 7 , wherein
multiple bits of data that are read by a unit of read in the concurrent read operation include the same data.