P-type control gate in non-volatile storage and methods for forming same
View Patent ↗Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.
1. A method of forming a memory array, the method comprising:
forming floating gates of non-volatile storage elements and lower portions of control gates of transistors from an n-type semiconductor;
forming lower portions of control gates of the non-volatile storage elements from a p-type semiconductor; and
forming upper portions of the control gates of the non-volatile storage elements and upper portions of the control gates of the transistors, including depositing n-type semiconductor for both the upper portions of the control gates of the non-volatile storage elements and upper portions of the control gates of the transistors in the same process step.
2. The method of claim 1 , wherein the forming control gates of the non-volatile storage elements and the forming control gates of the transistors include:
depositing the p-type semiconductor in regions where the non-volatile storage elements and regions where the transistors are to be formed; and
etching the p-type semiconductor in the regions where the transistors are to be formed to expose the n-type semiconductor of the lower portions of the control gates of the transistors.
3. The method of claim 1 , further comprising:
forming a conductive barrier layer between the lower portions and the upper portions of the control gates of the non-volatile storage elements.
4. The method of claim 1 , wherein the forming lower portions of the control gates of the non-volatile storage elements and the forming upper portions of the control gates of the non-volatile storage elements include:
highly doping the upper portions and lower portions of the control gates of the non-volatile storage elements such that p-n junctions between the upper portions and the lower portions of the control gates of the non-volatile storage elements will break down during programming.
5. The method of claim 1 , wherein the forming lower portions of the control gates of the non-volatile storage elements and the forming upper portions of the control gates of the non-volatile storage elements include:
forming a silicide of the entire upper portions of the control gates of the non-volatile storage elements.
6. The method of claim 1 , wherein the forming control gates of the non-volatile storage elements and the forming control gates of the transistors includes:
depositing the p-type semiconductor in regions where the non-volatile storage elements and regions where the transistors are to be formed; and
etching the p-type semiconductor in the regions where the transistors are to be formed to expose the n-type semiconductor for the lower portions of transistor control gates in regions where the transistors are to be formed.
7. The method of claim 1 , wherein the n-type semiconductor for the floating gates of the non-volatile storage elements includes polysilicon.
8. The method of claim 7 , wherein the n-type semiconductor for the upper portions of the control gates of the non-volatile storage elements and the upper portions of the control gates of transistors includes polysilicon.
9. A method of forming a memory array, the method comprising:
forming a first region of polysilicon to be used for floating gates of non-volatile storage elements and lower portions of control gates of transistors, the first region of polysilicon is n-type polysilicon;
forming an inter-poly dielectric over the first region of polysilicon;
forming a second region of polysilicon over the inter-poly dielectric, the second region of polysilicon is formed in regions in which the non-volatile storage elements and the transistors are to be formed, the second region of polysilicon is p-type polysilicon;
removing portions of the second region of polysilicon in the regions in which the transistors are to be formed to expose the first region of polysilicon;
depositing n-type polysilicon over the second region of polysilicon while depositing n-type polysilicon over the exposed first region of polysilicon; and
etching the first region of polysilicon, the inter-poly dielectric, the second region of polysilicon, and the n-type polysilicon over the second region and the exposed first region to form control gates for the non-volatile storage elements from the second region of polysilicon and the n-type polysilicon over the second region and to form control gates for the transistors from the first region of polysilicon and the n-type polysilicon over the exposed first region.
10. The method of claim 9 , further comprising:
forming a conductive barrier material between the second region of polysilicon and the n-type polysilicon over the second region at least in the control gates of the non-volatile storage elements.
11. The method of claim 9 , further comprising:
highly doping the n-type polysilicon over the second region and the p-type polysilicon of the second region such that p-n junctions between upper portions and lower portions of the control gates of the non-volatile storage elements will break down during programming.
12. The method of claim 9 , further comprising:
forming a silicide of the n-type polysilicon over the second region.
13. A method of forming a memory array, the method comprising:
forming floating gates of non-volatile storage elements and lower portions of control gates of transistors from an n-type semiconductor;
forming lower portions of control gates of the non-volatile storage elements from a p-type semiconductor; and
forming upper portions of the control gates of the non-volatile storage elements and upper portions of the control gates of the transistors from p-type semiconductor, including depositing material for both the upper portions of the control gates of the non-volatile storage elements and upper portions of the control gates of the transistors in the same process step.
14. The method of claim 13 , further comprising:
forming a conductive barrier layer between the n-type semiconductor and the p-type semiconductor in the control gates of the transistors.
15. The method of claim 13 , wherein the depositing material for both the upper portions of the control gates of the non-volatile storage elements and the upper portions of the control gates of the transistors in the same process step includes depositing a p-type semiconductor for the upper portions of the control gates of the non-volatile storage elements and the upper portions of the control gates of the transistors in the same process step.
16. The method of claim 13 , further comprising:
counter-doping the upper portions of the control gates of the transistors with an n-type dopant.