Semiconductor structure with gate structure, source/drain region and recess filling with epitaxial layer
View Patent ↗A semiconductor structure comprises a substrate, a gate structure, at least a source/drain region, a recess and an epitaxial layer. The substrate includes an up surface. A gate structure is located on the upper surface. The source/drain region is located within the substrate beside the gate structure. The recess is located within the source/drain region. The epitaxial layer fills the recess, and the cross-sectional profile of the epitaxial layer is an octagon.
1. A semiconductor structure, comprising:
a substrate, including an up surface;
a gate structure, located on the up surface;
at least a source/drain region, located within the substrate beside the gate structure;
a first recess located within the source/drain region, wherein the first recess at least has a vertical sidewall, a slanted sidewall and a flat-bottomed surface, wherein the vertical sidewall is disposed directly under the gate structure; and
an epitaxial layer filling the first recess.
2. The semiconductor structure of claim 1 , wherein the flat-bottomed is parallel to the up surface.
3. The semiconductor structure of claim 1 , wherein the substrate includes a single crystalline silicon, and the crystal planes of the substrate is composed of the <100> planes, the <110> planes, and the <111> planes of the silicon.
4. The semiconductor structure of claim 3 , wherein the up surface is oriented along the <100> planes, and the slanted sidewall is along the <111> planes.
5. The semiconductor structure of claim 3 , wherein the up surface is oriented along the <110> planes, and the slanted sidewall is along the <111> planes.
6. The semiconductor structure of claim 1 , wherein the gate structure comprises a gate dielectric layer, a gate electrode located on the gate dielectric layer, and a spacer surrounding the gate electrode and the gate dielectric layer.
7. The semiconductor structure of claim 6 , wherein the vertical sidewall is located beneath the gate dielectric layer.
8. The semiconductor structure of claim 6 , wherein the vertical sidewall is located beneath the spacer.
9. The semiconductor structure of claim 1 , further comprising a second recess located within the substrate and on the side of the gate structure opposite to the first recess.
10. The semiconductor structure of claim 9 , wherein a vertical sidewall of the second recess is located beneath the gate structure.
11. The semiconductor structure of claim 10 , further comprising a gate channel within the substrate beneath the gate structure and between the slanted sidewall of the first recess and a slanted sidewall of the second recess.
12. The semiconductor structure of claim 1 , wherein top of the vertical sidewall is lower than the up surface of the substrate.