Betavoltaic battery with a shallow junction and a method for making same
This is a novel SiC betavoltaic device (as an example) which comprises one or more “ultra shallow” P+N − SiC junctions and a pillared or planar device surface (as an example). Junctions are deemed “ultra shallow”, since the thin junction layer (which is proximal to the device's radioactive source) is only 300 nm to 5 nm thick (as an example). In one example, tritium is used as a fuel source. In other embodiments, radioisotopes (such as Nickel-63, promethium or phosphorus-33) may be used. Low energy beta sources, such as tritium, emit low energy beta-electrons that penetrate very shallow distances (as shallow as 5 nm) in semiconductors, including SiC, and can result in electron-hole pair creation near the surface of a semiconductor device rather than pair creation in a device's depletion region. By contrast, as a high energy electron penetrates a semiconductor device surface, such as a diode surface, it produces electron hole-pairs that can be collected at (by drift) and near (by diffusion) the depletion region of the device. This is a betavoltaic device, made of ultra-shallow junctions, which allows such penetration of emitted lower energy electrons, thus, reducing or eliminating losses through electron-hole pair recombination at the surface.
1. A semiconductor processing method, said method comprising:
dipping a semiconductor substrate into a hot liquid comprising elements Si, C, and Al, for a period of time equal to t,
wherein t is equal to (L/R), wherein L is thickness of a grown p-type layer, and R is rate of growth for said grown p-type layer;
wherein L is smaller than thickness of said semiconductor substrate;
pulling out said semiconductor substrate from said hot liquid; and
attaching said grown p-type layer to a piece of radioisotope material.
2. The semiconductor processing method as recited in claim 1 , wherein one side of said semiconductor substrate is an N-type material.
3. The semiconductor processing method as recited in claim 1 , wherein one side of said semiconductor substrate is a lightly-doped material.
4. The semiconductor processing method as recited in claim 1 , wherein said semiconductor substrate is N-type material.
5. The semiconductor processing method as recited in claim 1 , wherein said semiconductor substrate is a lightly-doped material.
6. The semiconductor processing method as recited in claim 1 , wherein said semiconductor substrate is from group IV elements.
7. The semiconductor processing method as recited in claim 1 , wherein said semiconductor substrate is from group III-V elements.
8. The semiconductor processing method as recited in claim 1 , wherein said semiconductor substrate is SiC.
9. The semiconductor processing method as recited in claim 1 , wherein temperature of said hot liquid is between 400 degrees C. to 1200 degrees C.
10. The semiconductor processing method as recited in claim 1 , wherein doping of said semiconductor substrate is smaller than doping of said grown p-type layer.
11. The semiconductor processing method as recited in claim 1 , wherein said grown p-type layer is highly doped.
12. The semiconductor processing method as recited in claim 1 , wherein doping of said grown p-type layer is highly degenerate.
13. The semiconductor processing method as recited in claim 1 , wherein thickness of said grown p-type layer is 5 nm to 300 nm.
14. The semiconductor processing method as recited in claim 1 , wherein said grown p-type layer is doped with Al.
15. The semiconductor processing method as recited in claim 1 , wherein said grown p-type layer is doped at carrier concentrations of between a range of 10 18 cm −3 to a few times 10 20 cm −3 .
16. The semiconductor processing method as recited in claim 1 , wherein relative concentration of said elements Si, C, and Al are 94.5%, 0.5% and 5%, respectively.
17. The semiconductor processing method as recited in claim 1 , wherein relative concentration of said elements Si, C, and Al are less than 95%, 3% and 30%, respectively.
18. The semiconductor processing method as recited in claim 1 , wherein Ge is added with Si, C and Al, with a concentration of less than 95%.
19. The semiconductor processing method as recited in claim 1 , wherein said grown p-type layer is on planar SiC.
20. The semiconductor processing method as recited in claim 1 , wherein said grown p-type layer is on SiC with pillars.
21. The semiconductor processing method as recited in claim 1 , wherein said semiconductor substrate is integrated with a Si substrate.
22. The semiconductor processing method as recited in claim 1 , wherein said grown p-type layer is on both sides of said semiconductor substrate.
23. The semiconductor processing method as recited in claim 1 , wherein said semiconductor substrate has one or more grooves on one or both sides of said semiconductor substrate.
24. The semiconductor processing method as recited in claim 23 , wherein said one or more grooves are curved, V-shaped, or zig-zag shaped.
25. A semiconductor processing method, said method comprising:
dipping a semiconductor substrate into a hot liquid comprising elements Si, C, and Al, for a period of time equal to t,
wherein t is equal to (L/R), wherein L is thickness of a grown p-type layer, and R is rate of growth for said grown p-type layer;
wherein L is smaller than thickness of said semiconductor substrate;
pulling out said semiconductor substrate from said hot liquid; and
positioning said grown p-type layer in vicinity of a piece of radioisotope material.
26. The semiconductor processing method as recited in claim 25 , wherein said radioisotope material is tritium.