Observing an internal link via an existing port for system on chip devices
Methods and apparatus relating to observing an internal link via an existing port for System On Chip (SOC) devices are described. In one embodiment, a logic within an SOC device may allow an external logic analyzer to observe communication between a first and second component of the SOC through an existing (e.g., shared and/or non-dedicated) interface. Other embodiments are also disclosed.
1. A System On Chip (SOC) device comprising:
a first component coupled to a second component via an internal link, wherein the first and second components are to communicate via the internal link without use of any analog front ends; and
logic to enable communication between the SOC device and an external link coupled to the SOC device, wherein the logic is to comprise a test controller to cause monitoring of operations of one or more components of the SOC device or cause monitoring of communications between the one or more components of the SOC device in response to a command, wherein the test controller is to cause selection of input signals of a first multiplexer and a second multiplexer, the first multiplexer having a first input coupled to a transmit portion of the internal link and a second input coupled to a receive portion of the internal link, the second multiplexer having a first input coupled to an output of the first multiplexer and a second input coupled to the external link.
2. The SOC device of claim 1 , wherein the command is to be transmitted by a device external to the SOC device.
3. The SOC device of claim 1 , wherein the command is to be transmitted by a logic analyzer that is external to the SOC device.
4. The SOC device of claim 1 , wherein the command is to be transmitted via a non-dedicated interface of the SOC device.
5. The SOC device of claim 1 , wherein the logic is to comprise a plurality of synchronization buffers to transfer data between a first clock domain and a second clock domain.
6. The SOC device of claim 1 , wherein the logic is to comprise the first and second multiplexers whose inputs are to be selected based on a plurality of signals to be generated by the test controller.
7. The SOC device of claim 1 , wherein the logic is to comprise a transaction layer.
8. The SOC device of claim 1 , wherein the logic is to comprise a common block.
9. The SOC device of claim 1 , wherein the logic is to comprise an analog front end.
10. The SOC device of claim 1 , wherein at least one of the first component or the second component are to comprise a processor having one or more processor cores.
11. The SOC device of claim 1 , further comprising a processor having one or more processor cores, wherein the processor is to comprise the logic.
12. A method comprising:
establishing communication between a first component and a second component via an internal link and without use of any analog front ends; and
enabling communication between a SOC device, which comprises the first and second component, and an external link coupled to the SOC device; and
causing monitoring of operations of one or more components of the SOC device or causing monitoring of communications between the one or more components of the SOC device in response to a command, wherein the test controller causes selection of input signals of a first multiplexer and a second multiplexer, the first multiplexer having a first input coupled to a transmit portion of the internal link and a second input coupled to a receive portion of the internal link, the second multiplexer having a first input coupled to an output of the first multiplexer and a second input coupled to the external link.
13. The method of claim 12 , further comprising transmitted the command from a device external to the SOC device.
14. The method of claim 12 , further comprising transmitting the command from a logic analyzer that is external to the SOC device.
15. The method of claim 12 , further comprising transmitting the command via a non-dedicated interface of the SOC device.
16. A system comprising:
a plurality of synchronization buffers to transfer data between a first clock domain and a second clock domain;
a first component;
a second component coupled to the first component via an internal link, wherein the first and second components are to communicate via the internal link without use of any analog front ends; and
logic to enable communication between the SOC device and an external link coupled to the SOC device, wherein the logic is to comprise a test controller to cause monitoring of operations of one or more components of the SOC device or cause monitoring of communications between the one or more components of the SOC device in response to a command, wherein the test controller is to cause selection of input signals of a first multiplexer and a second multiplexer, the first multiplexer having a first input coupled to a transmit portion of the internal link and a second input coupled to a receive portion of the internal link, the second multiplexer having a first input coupled to an output of the first multiplexer and a second input coupled to the external link.
17. The system of claim 16 , wherein the command is to be transmitted by a device external to the SOC device or by a logic analyzer that is external to the SOC device.
18. The system of claim 16 , wherein the command is to be transmitted via a non-dedicated interface of the SOC device.
19. The system of claim 16 , wherein the logic is to comprise the plurality of synchronization buffers.
20. The system of claim 16 , wherein the logic is to comprise the first and second multiplexers whose inputs are to be selected based on a plurality of signals to be generated by the test controller.