Method and apparatus for reducing processor cache pollution caused by aggressive prefetching
View Patent ↗A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.
1. A method for controlling a first and second cache, comprising:
receiving a cache entry in the first cache;
identifying the received cache entry as having an untouched status;
updating the untouched status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry;
casting out the cache entry according to a preselected cache line replacement algorithm; and
controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
2. A method, as set forth in claim 1 , wherein controlling storage of the cast out cache entry further comprises storing the cast out cache entry in the second cache in response to the cast out cache entry having an accessed status.
3. A method, as set forth in claim 1 , wherein controlling storage of the cast out cache entry further comprises preventing the cast out cache entry from being stored in the second cache in response to the cast out cache entry having an untouched status.
4. A method, as set forth in claim 1 , wherein controlling storage of the cast out cache entry further comprises storing the cast out cache entry in the second cache and identifying the cast out cache entry as being the least recently used entry in the second cache in response to the cast out cache entry having an untouched status.
5. A memory system, comprising:
a first-level cache;
a second-level cache;
a first-level cache controller adapted for identifying a received cache entry as having an untouched status, updating the untouched status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry, and casting out the cache entry according to a preselected cache line replacement algorithm; and
a second-level cache controller for controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
6. A memory system, as set forth in claim 5 , wherein the second-level cache controller controls storage of the cast out cache entry by storing the cast out cache entry in the second cache in response to the cast out cache entry having an accessed status.
7. A memory system, as set forth in claim 5 , wherein the second-level cache controller controls storage of the cast out cache entry by preventing the cast out cache entry from being stored in the second cache in response to the cast out cache entry having an untouched status.
8. A memory system, as set forth in claim 5 , wherein the second-level cache controller controls storage of the cast out cache entry by storing the cast out cache entry in the second cache and identifying the cast out cache entry as being the least recently used entry in the second cache in response to the cast out cache entry having an untouched status.
9. A memory system, as set forth in claim 5 , wherein the first-level cache controller is adapted to deliver the status of the cast out cache entry to the second-level cache-controller in response to the cache entry being cast out of the first-level cache.
10. A microprocessor, comprising:
a core;
a first-level cache;
a second-level cache;
a first-level cache controller adapted for identifying a received cache entry as having an untouched status, updating the status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry from the core, and casting out the cache entry according to a preselected cache line replacement algorithm; and
a second-level cache controller for controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
11. A microprocessor, as set forth in claim 10 , wherein the second-level cache controller controls storage of the cast out cache entry by storing the cast out cache entry in the second cache in response to the cast out cache entry having an accessed status.
12. A microprocessor, as set forth in claim 10 , wherein the second-level cache controller controls storage of the cast out cache entry by preventing the cast out cache entry from being stored in the second cache in response to the cast out cache entry having an untouched status.
13. A microprocessor, as set forth in claim 10 , wherein the second-level cache controller controls storage of the cast out cache entry by storing the cast out cache entry in the second cache and identifying the cast out cache entry as being the least recently used entry in the second cache in response to the cast out cache entry having an untouched status.
14. A microprocessor, as set forth in claim 10 , wherein the first-level cache controller is adapted to deliver the status of the cast out cache entry to the second-level cache-controller in response to the cache entry being cast out of the first-level cache.
15. A computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create a memory system, comprising:
a first-level cache;
a second-level cache;
a first-level cache controller adapted for identifying a received cache entry as having an untouched status, updating the untouched status of the cache entry to accessed in response to receiving a request for at least a portion of the cache entry, and casting out the cache entry according to a preselected cache line replacement algorithm; and
a second-level cache controller for controlling storage of the cast out cache entry in the second cache according to the status of the cast out cache entry.
16. A computer readable storage device, as set forth in claim 15 , wherein the second-level cache controller controls storage of the cast out cache entry by storing the cast out cache entry in the second cache in response to the cast out cache entry having an accessed status.
17. A computer readable storage device, as set forth in claim 15 , wherein the second-level cache controller controls storage of the cast out cache entry by preventing the cast out cache entry from being stored in the second cache in response to the cast out cache entry having an untouched status.
18. A computer readable storage device, as set forth in claim 15 , wherein the second-level cache controller controls storage of the cast out cache entry by storing the cast out cache entry in the second cache and identifying the cast out cache entry as being the least recently used entry in the second cache in response to the cast out cache entry having an untouched status.
19. A computer readable storage device, as set forth in claim 15 , wherein the first-level cache controller is adapted to deliver the status of the cast out cache entry to the second-level cache-controller in response to the cache entry being cast out of the first-level cache.