System and method for integrated circuits with cylindrical gate structures
A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel.
1. A semiconductor device comprising:
a substrate;
a first insulation layer overlaying the substrate;
an elongated semiconductor region overlying the first insulation layer along a first direction, the elongated semiconductor region including a first end section, a middle section, and a second end section;
a source region being within the first end section;
a drain region being within the second end section;
a channel region being within the middle section, the channel region connecting the source region and the drain region, the channel region, the source region, and the drain region being characterized by a substantially cylindrical shape having a radius and a length, the source region and the drain region overlaying an undercut structure formed by a portion of the first insulation layer, the undercut structure having a width less than a width of the cylindrical shape, the undercut structure being absent underneath the channel region;
a second insulation layer surrounding the cylindrical channel region; and
a gate electrode overlaying the second insulation layer all around the channel region and overlaying the first insulation layer along a second direction, the second direction being substantially perpendicular to the first direction,
wherein the channel region comprises a first dopant and the source/drain regions comprise a second dopant, the first dopant being characterized by a first polarity, the second dopant being characterized by a second polarity, the first polarity being opposite from the second polarity.
2. The device of claim 1 wherein the elongated semiconductor region comprises a material doped through threshold-adjustment ion implantation.
3. The device of claim 2 wherein the material includes silicon.
4. The device of claim 2 wherein the material includes SiGe mixture.
5. The device of claim 1 wherein each of the source and drain regions of the elongated semiconductor region overlays an undercut structure of the first insulation layer.
6. The device of claim 1 wherein the channel region is not directly in contact with the first insulation layer.
7. The device of claim 1 wherein the radius of the channel region ranges from 2 nm to 25 nm and the length of the channel region ranges from 5 nm to 50 nm.
8. The device of claim 1 wherein the first insulation layer comprises silicon oxide.
9. The device of claim 1 wherein the second insulator layer surrounding the cylindrical channel region has a nominal thickness ranging from 1 nm to 3 nm.
10. The device of claim 9 wherein the second insulation layer comprises at least one dielectric material of aluminum oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium oxide.
11. The device of claim 1 wherein the gate electrode is characterized by a length in the first direction, the length being substantially equal to the length of the channel region.
12. The device of claim 11 wherein the gate electrode is electrically isolated from each of the source region and the drain region by an insulation spacer.
13. The device of claim 12 wherein the insulation spacer comprises an oxide/nitride/oxide (ONO) layer.
14. The device of claim 1 wherein the second dopant comprises an n-type impurity.
15. The semiconductor device of claim 1 wherein further comprising:
a first contact hole directly above the cylindrical source region;
a second contract hole directly above the cylindrical drain region; and
a third contact hole offset from the cylindrical channel region.
16. A semiconductor device comprising:
a substrate;
a first insulation layer overlaying the substrate;
an elongated semiconductor region overlying the first insulation layer along a first direction, the elongated semiconductor region including a first end section, a middle section, and a second end section;
a source region being within the first end section;
a drain region being within the second end section;
a channel region being within the middle section, the channel region connecting the source region and the drain region, the channel region, the source region, and the drain region being characterized by a substantially cylindrical shape having a radius and a length, the source region and the drain region overlaying an undercut structure formed by a portion of the first insulation layer, the undercut structure having a width less than a width of the cylindrical shape, the undercut structure being absent underneath the channel region;
a second insulation layer surrounding the cylindrical channel region; and
a gate electrode overlaying the second insulation layer all around the channel region and overlaying the first insulation layer along a second direction, the second direction being substantially perpendicular to the first direction,
wherein the channel region comprises a first dopant and the source/drain regions comprise a second dopant, the first dopant and the second dopant being characterized by a same polarity, wherein a dopant concentration in the source/drain regions is higher than that in the channel region.
17. The semiconductor device of claim 16 wherein the first and second dopants comprise a p-type impurity.
18. The semiconductor device of claim 16 wherein the gate electrode is electrically isolated from each of the source region and the drain region by an insulation spacer, the insulation spacer comprising an oxide/nitride/oxide (ONO) layer.
19. The semiconductor device of claim 16 wherein the gate electrode comprises a metal material.
20. The semiconductor device of claim 16 wherein a current flows from the source region to the drain region across the channel region when a voltage is applied to the gate electrode.
21. The semiconductor device of claim 16 further comprising:
a first contact hole directly above the cylindrical source region;
a second contract hole directly above the cylindrical drain region; and
a third contact hole offset from the cylindrical channel region.