IP Library › Patent Application 12896471
Patent Application
App. No. 12/896,471

MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT

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Quick Facts
Patent No.
US None
App. No.
12/896,471
Abstract

A manufacturing method of a semiconductor element formed by multi-layering on a substrate so as to include an n-type semiconductor and a p-type semiconductor. The method includes a process of sputtering, with a gas including a group V element, at least two targets (a first target 21 and a second target 22 ) made of group III elements that are different from each other, thereby to form a film of a III-V compound semiconductor on the substrate 110.

Claims (12)

1 . A manufacturing method of a semiconductor element formed by multi-layering on a substrate so as to include an n-type semiconductor and a p-type semiconductor,

the method comprising a process of sputtering, with a gas including a group V element, at least two targets made of group III elements that are different from each other, thereby to form a film of a III-V compound semiconductor on the substrate.

2 . The manufacturing method of a semiconductor element according to claim 1 , wherein a shield panel is included between the at least two targets made of the group III elements that are different from each other.

3 . The manufacturing method of a semiconductor element according to claim 1 , wherein a composition ratio of the compound semiconductor is set by sputtering power supplied to each of the at least two targets made of the group III elements.

4 . The manufacturing method of a semiconductor element according to claim 1 , wherein the substrate is alternately located at each of positions respectively facing the at least two targets, and thereby the film of the compound semiconductor is formed.

5 . The manufacturing method of a semiconductor element according to claim 1 , wherein the group III elements are indium (In) and gallium (Ga), the group V element is nitrogen (N), and the compound semiconductor is In x Ga 1−x N (where 0<x<1).

6 . The manufacturing method of a semiconductor element according to claim 5 , wherein the composition ratio x of indium (In) in the compound semiconductor is set, by sputtering power P 1 supplied to one of the targets made of the indium (In) and sputtering power P 2 supplied to one of the targets made of the gallium (Ga), as follows

x= 1.21 ×P 1/( P 1 +P 2).

7 . The manufacturing method of a semiconductor element according to claim 5 , wherein the composition ratio x of indium (In) in the compound semiconductor is in a range of not less than 0.7, and substrate temperature is set to be not less than 150 degrees C. and not more than 400 degrees C.

8 . The manufacturing method of a semiconductor element according to claim 5 , wherein the composition ratio x of indium (In) in the compound semiconductor is in a range of not less than 0.3 and less than 0.7, and substrate temperature is set to be more than 400 degrees C. and not more than 800 degrees C.

9 . The manufacturing method of a semiconductor element according to claim 1 , wherein the substrate is formed of any one of sapphire, silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), quartz and amorphous solid (glass).

10 . The manufacturing method of a semiconductor element according to claim 1 , wherein the semiconductor element is any one of a semiconductor light emitter and a semiconductor photo detector.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2012
From: SHOWA DENKO K.K.
To: TOYODA GOSEI CO., LTD.
Reel/Frame 029400/0672 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2010
From: KAJI, HIROAKI
To: SHOWA DENKO K.K.
Reel/Frame 025490/0560 →