Single-event upset immune static random access memory cell circuit
View Patent ↗A circuit and method are provided in which a six-transistor (6-T) SRAM memory cell is hardened to single-event upsets by adding isolation-field effect transistors (“iso-fets”) connected between the reference voltage Vdd and the field-effect transistors (“fets”) respectively corresponding to first and second inverters of the memory cell. According to certain embodiments, the control gates of first and second P-iso-fets are respectively tied to the control gates of first and second pull-up P-fets. According to certain embodiments, first and second N-iso-fets are connected between the output nodes of the memory cell and the pull-down N-fets respectively corresponding to the first and second inverters. The control gates of the first and second N-iso-fets are respectively tied to the control gates of the first and second pull-down N-fets. Again according to certain embodiments, one or more of the iso-fets are physically removed from the proximity of other transistors which comprise the memory cell.
1. A memory cell disposed in a substrate, comprising:
first and second output nodes;
a first P-type transistor having a first conduction node connected to a first reference voltage, a control node connected to said first output node, and a second conduction node connected to said second output node;
a second P-type transistor having a first conduction node connected to said first reference voltage, a control node connected to said second output node, and a second conduction node connected to said first output node;
first and second N-type transistors connected in series between the first output node and a second reference voltage, each of said first and second N-type transistors having a respective control node connected to said second output node;
third and fourth N-type transistors connected in series between the second output node and said second reference voltage, each of said third and fourth N-type transistors having a respective control node connected to said first output node, wherein said first and third N-type transistors are physically formed at least two microns distant from each of said first and second P-type transistors and said second and fourth N-type transistors; and
a first capacitive element coupled between said second reference voltage and the control nodes of at least the first, second and third N-type transistors.
2. The memory cell of claim 1 , further comprising a second capacitive element coupled between said second reference voltage and the control nodes of at least the first and second P-type field transistors.