Method of fabricating a semiconductor device and structure

1. A method to fabricate a semiconductor device, comprising the sequence of:

implanting one or more regions on a semiconductor wafer forming a doped layer;

performing a first transfer of said doped layer onto a carrier; and then performing a second transfer of said doped layer from said carrier to a target wafer; and then

etching said one or more regions of said doped layer to form transistors on said doped layer.

2. A method according to claim 1 wherein said first transfer comprises ion-cut.

3. A method according to claim 1 , further comprising high temperature annealing of said doped layer after said first transfer and before said second transfer and wherein said high temperature is greater than 400° C.

4. A method according to claim 1 , further comprising oxidation and etch-back smoothing.

5. A method according to claim 1 , further comprising replacement of one or more gates of said transistors.

6. A method according to claim 1 wherein said transistors comprise recessed-channel-transistors.

7. A method according to claim 1 wherein said transistors comprise at least one P type transistor and one N type transistor.

8. A method according to claim 1 wherein said transistors comprise Finfet transistors.

9. A method according to claim 1 wherein said transistors comprise junction-less transistors.

10. A method to fabricate a semiconductor device, comprising the sequence of:

implanting one or more regions in a semiconductor wafer to form a doped regions layer;

performing a first layer transfer of said doped regions layer using ion-cut onto a carrier; and then

performing a second layer transfer of said doped regions layer from said carrier onto a target wafer.

11. A method according to claim 10 , further comprising annealing of said doped regions layer at higher than 400° C. temperature after said first transfer and before said second transfer.

12. A method according to claim 10 , further comprising forming horizontally oriented transistors on said doped regions layer after said second layer transfer.

13. A method according to claim 10 , further comprising forming junction-less transistors on said doped regions layer after said second layer transfer.

14. A method according to claim 10 , further comprising performing gate replacement.

15. A method according to claim 10 , further comprising oxidation and etch-back smoothing.

16. A method according to claim 10 , further comprising etching one or more regions of said doped regions layer to form transistors on said doped regions layer.

17. A method according to claim 16 wherein said transistors comprises a Finfet type transistor.

18. A method according to claim 10 wherein said performing a second layer transfer comprises etching.

19. A method to fabricate a semiconductor device, comprising the sequence of:

implanting one or more regions in a semiconductor wafer to partially form transistors;

performing a first layer transfer from said semiconductor wafer onto a carrier; and then

performing a greater than 400° C. temperature anneal, and then

performing a second layer transfer from said carrier onto a target wafer.

20. A method according to claim 19 wherein said first layer transfer comprises ion-cut.

21. A method according to claim 19 further comprising forming transistors after said second layer transfer.

22. A method according to claim 19 further comprising forming junction-less transistors.

23. A method according to claim 19 further comprising performing gate replacement.

24. A method according to claim 19 further comprising oxidation and etch-back smoothing.

25. A method according to claim 19 further comprising etching of one or more regions to form transistors after said second layer transfer.

26. A method according to claim 19 further comprising forming Finfet transistors.

27. A method according to claim 19 wherein said performing a second layer transfer comprises etching.

28. A method according to claim 19 wherein said performing a second layer transfer comprises ion-cut.