Resistive memory
View Patent ↗A memory device includes an array of memory structures disposed in rows and columns and constructed over a substrate, each memory structure comprising a first signal electrode, a second signal electrode, and a resistive layer coupled to the first signal electrode and the second signal electrode; a plurality of word lines connected to the first signal electrodes of a row of memory cells; and a plurality of bit lines connected to the second signal electrodes of a column of memory cells.
1. A memory device, comprising:
an array of memory structures disposed in rows and columns and constructed over a substrate, each memory structure comprising a first signal electrode, a second signal electrode, and a resistive layer coupled to the first signal electrode and the second signal electrode;
a plurality of word lines connected to the first signal electrodes of a row of memory cells; and
a plurality of bit lines connected to the second signal electrodes of a column of memory cells and wherein the resistive layer comprises two resistive elements that in combination have a zero temperature coefficient.
2. The memory device of claim 1 , wherein the resistive layer comprises memory elements.
3. The memory device of claim 1 , further comprising a driver circuit for selectively controlling the first signal electrodes or the second signal electrodes.
4. The memory device of claim 3 , wherein the circuit includes one or more of a Y gate, a sense amplifier, an input-output buffer, an X address decoder, a Y address decoder, and an address buffer.
5. The memory device of claim 1 , wherein the substrate includes a silicon-on-insulator wafer.
6. The memory device of claim 1 , wherein the resistive layer is spin-coated over the substrate wherein first signal electrodes and the second signal electrodes are constructed.
7. The memory device of claim 1 , wherein the resistive layer includes stacked layers.
8. The memory device of claim 1 , wherein the resistive layer forms transistors.
9. The memory device of claim 1 , wherein the resistive layer store data at intersections of resistors.
10. The memory device of claim 1 , further comprising an array of redundant memory elements.
11. The memory device of claim 10 , wherein the redundant array is a row or a column of redundant resistive-elements.
12. The memory device of claim 1 , comprising magnetic elements or optical elements coupled to the memory.
13. The memory device of claim 1 , further comprising memory devices forming a plurality of memory hierarchy to optimize data access speed.
14. A memory electronic device, comprising:
a substrate;
a first layer fabricated using semiconductor fabrication techniques;
a second layer formed above the first layer, the second layer having one or more resistive-bonding areas;
one or more resistive memory elements self-assembled to the second layer resistive bonding areas and wherein the resistive memory elements comprises two resistive elements that in combination have a zero temperature coefficient.
15. The device of claim 14 , wherein the resistive-elements is disposed in an array pattern.
16. The device of claim 14 , wherein the resistive-elements are spin-coated on the second layer.
17. A memory electronic device, comprising:
a substrate;
a first layer fabricated using semiconductor fabrication techniques;
a second layer formed above the first layer, the second layer having one or more resistive-bonding areas;
a plurality of resistive memory elements coupled to the second layer resistive bonding areas, wherein each resistive memory element has two resistive elements that in combination has a zero temperature coefficient.
18. The device of claim 17 , wherein a first resistive element comprises a positive temperature coefficient and the second resistive element has a negative temperature coefficient.
19. The device of claim 17 , wherein the temperature coefficient is selected such that a series or parallel combination of the two elements results in a resistive element having zero temperature coefficient.