Architecture guided optimal system precision definition algorithm for custom integrated circuit
Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
1. A method to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC), comprising:
a. determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio;
b. determining an optimal number representation format based on a cost function that includes hardware area cost and power cost associated with a predetermined bit precision arithmetic and taking into consideration a signal to noise ratio (SNR) and an estimated precision needed to accommodate a set of arithmetic operations with minimal decrease in the SNR, including:
identifying arithmetic operations on variables using a static parsing of a system model description;
estimating a precision needed to accommodate the arithmetic operations with minimal decrease in SNR;
evaluating the cost function and if the cost is higher than a threshold, marching along a variable axis that decreases the cost;
c. automatically and iteratively generating a processor architecture customized to the optimal number representation format; and
d. synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication by using a computer.
2. The method of claim 1 , comprising using a memory storage requirement for the number representation as an optimization cost.
3. The method of claim 1 , comprising determining real-time performance for the number representation as an optimization cost.
4. The method of claim 1 , comprising determining the number of bits needed in the number representation format.
5. The method of claim 4 , wherein the number of bits comprises an odd number of bits.
6. The method of claim 1 , comprising determining if the selected number representation format pushes an input signal value below a noise floor.
7. The method of claim 1 , comprising evaluating the optimal number representation format using a cost function and marching along a variable axis to meet a system cost requirement if the cost function evaluation exceeds a desired cost.
8. The method of claim 1 , comprising inserting a scaling operation in the model or code to achieve a desired cost.
9. A system to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC), comprising a processor executing computer readable code to:
a. determine a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio;
b. determine the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic and taking into consideration a signal to noise ratio (SNR) and an estimated precision needed to accommodate a set of arithmetic operations with minimal decrease in the SNR, including:
identifying arithmetic operations on variables using a static parsing of a system model description;
estimating a precision needed to accommodate the arithmetic operations with minimal decrease in SNR;
evaluating the cost function and if the cost is higher than a threshold, marching along a variable axis that decreases the cost;
c. automatically and iteratively generate a processor architecture customized to the optimal number representation format; and
d. synthesize the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
10. The system of claim 9 , comprising code to use a memory storage requirement for the number representation as one optimization cost.
11. The system of claim 9 , comprising code to determine real-time performance for the number representation as one optimization cost.
12. The system of claim 9 , comprising code to determine the number of bits needed in the number representation format.
13. The system of claim 12 , wherein the number of bits comprises an odd number of bits.
14. The system of claim 9 , comprising code to determine if the selected number representation format pushes the required signal below a noise floor.
15. The system of claim 9 , comprising code to evaluate the optimal number representation format using a cost function and marching along a variable axis to meet a system cost requirement if the cost function evaluation exceeds a desired cost.
16. The system of claim 9 , comprising code to insert a scaling operation in the model or code to achieve a desired cost.