Predictive read channel configuration

1. A method of controlling a read operation of a solid state non-volatile memory, comprising:

performing a write operation involving pages of memory cells of a data unit;

storing time information of the write operation;

storing temperature information of the write operation;

determining one or more reference voltages to be used for reading data stored in the pages of the data unit using one or both of the write time information and the write temperature information; and

sending an output to the memory that includes information about the reference voltages to be used for reading the data stored in the pages of the data unit.

2. The method of claim 1 , wherein storing the write time information and the write temperature information comprises storing the write time information and the write temperature information in a data unit header within the data unit.

3. The method of claim 2 , further comprising updating the data unit header with write time information and write temperature information from one or more additional write operations.

4. The method of claim 3 , wherein updating the data unit header comprises updating the data unit header only if one or both of a write time and a write temperature of an additional write operation is beyond a predetermined value.

5. The method of claim 3 , further comprising modifying an update process used in updating the data unit header to increase or decrease an amount of information stored in the data unit header during the updating.

6. The method of claim 5 , further comprising triggering modification of the update process in response to diminished capacity of the data unit header or in response to a need for additional information based on an error rate of the pages.

7. The method of claim 2 , further comprising reconfiguring information previously stored in the data unit header, the reconfiguring including one or more of compressing, deleting, and combining the information previously stored in the data unit header.

8. The method of claim 1 , wherein the data unit comprises a garbage collection unit and performing the write operation comprises performing the write operation during garbage collection.

9. The method of claim 1 , wherein determining the reference voltages comprises compensating for one or both of charge leakage and disturb effects.

10. A method of configuring a read channel of a non-volatile solid state memory, comprising:

developing a historical profile that spans multiple write operations that write data to memory cells of a data unit, the historical profile including at least a number of erase/write cycles experienced by the data unit and temperature information of the data unit;

storing the historical profile;

determining configuration information using the historical profile, the configuration information used for configuring the read channel for a read operation of the memory cells of the data unit; and

sending an output to the memory, the output including the configuration information.

11. The method of claim 10 , wherein the temperature information includes one or both of an operating temperature of the data unit and a number of write operations within a temperature range.

12. The method of claim 10 , further comprising storing a log of a current write operation that includes one or both of write time information of the current write operation and write temperature information of the current write operation, wherein determining the configuration information includes one or both of determining reference voltages for the read operation using the write time information and the write temperature information and estimating an extent to which charge leakage has altered a threshold voltage of the memory cells.

13. A memory device, comprising:

a write operation control module configured to generate signals that control write operations of a memory, the write operations causing data to be stored in pages of memory cells of a data unit of the memory;

information acquisition circuitry configured to control acquisition and storage of write time information for each write operation and write temperature information for at least some of the write operations; and

read channel configuration circuitry configured to determine read channel configuration information to be used for read operations performed on the pages of the data unit, the read channel configuration circuitry configured to determine the configuration information using the write time information and the write temperature information, the read channel configuration circuitry further configured to output the configuration information to the memory.

14. The memory device of claim 13 , wherein the information acquisition circuitry is further configured to acquire an operating temperature of the data unit and the read channel configuration circuitry is configured to determine the configuration information using the operating temperature.

15. The memory device of claim 13 , wherein the information acquisition circuitry is configured to control storage of the write time information and the write temperature information in a data unit header within the data unit.

16. The memory device of claim 13 , wherein the data unit comprises a garbage collection unit and the write time information comprises a sequence number of the garbage collection unit.

17. The memory device of claim 13 , wherein the read channel configuration circuitry is configured to determine reference voltages that compensate for expected shifts in threshold voltages of the memory cells due to charge leakage according to a charge loss/gain model of the memory cells.

18. The memory device of claim 13 , wherein the information acquisition circuitry is configured to develop a historical profile that spans multiple write operations, the historical profile developed based on write time information and write temperature information from at least some of the multiple write operations.

19. The memory device of claim 18 , wherein the historical profile includes a number of erase/write cycles experienced by the data unit and a number of write operations performed with a temperature range.

20. The memory device of claim 13 , wherein the information acquisition circuitry is configured to adapt a process for storing the write time information and the write temperature information in response to reduced storage capacity for the write time information and the write temperature information.