Self-aligned memory cells and method for forming
View Patent ↗The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.
1. An electronic device comprising:
a substrate;
a first conductive region formed on said substrate;
an access device in electrical communication with said first conductive region, said access device having a pillar structure, said pillar structure having an exterior surface, said exterior surface including a sidewall surface and a top surface;
a first dielectric material in direct contact with said sidewall surface, said first dielectric material not contacting said first conductive region or said substrate; and
an electronic material in electrical communication with said access device.
2. The electronic device of claim 1 , wherein said access device is selected from the group consisting of a diode, a transistor, and a threshold switch.
3. The electronic device of claim 1 , wherein said pillar structure has a rectilinear cross-section.
4. The electronic device of claim 1 , wherein said pillar structure has a rounded cross-section.
5. The electronic device of claim 1 , wherein said access device directly contacts said first conductive region.
6. The electronic device of claim 5 , wherein said electronic material directly contacts said access device.
7. The electronic device of claim 1 , further comprising a barrier layer disposed between said first conductive region and said electronic material.
8. The electronic device of claim 1 , wherein said pillar structure comprises a plurality of layers.
9. The electronic device of claim 8 , wherein said first dielectric material is in direct contact with each layer of said plurality of layers.
10. The electronic device of claim 8 , wherein said plurality of layers includes a first layer in direct contact with said first conductive region and said first dielectric material is in direct contact with said first layer.
11. The electronic device of claim 10 , wherein said first layer is a barrier layer.
12. The electronic device of claim 10 , wherein said first layer comprises a semiconducting material.
13. The electronic device of claim 1 , wherein said first dielectric material circumscribes said access device.
14. The electronic device of claim 1 , wherein said sidewall surface of said access device is embedded in said first dielectric material.
15. The electronic device of claim 14 , wherein said top surface of said access device is recessed below the top surface of said first dielectric material.
16. The electronic device of claim 15 , wherein the top surface of said electronic material is recessed below the top surface of said first dielectric material.
17. The electronic device of claim 16 , further comprising a second conductive region, said second conductive region contacting said top surface of said electronic material.
18. The electronic device of claim 14 , wherein said electronic material contacts said top surface of said access device.
19. The electronic device of claim 18 , further comprising a second dielectric material, said second dielectric material contacting said electronic material and said first dielectric material.
20. The electronic device of claim 1 , further comprising a second dielectric material in direct contact with said first dielectric material.
21. The electronic device of claim 20 , wherein said second dielectric material circumscribes said first dielectric material.
22. The electronic device of claim 20 , wherein said second dielectric material directly contacts said first conductive region or said substrate.
23. The electronic device of claim 1 , wherein said electronic material is in electrical communication with said access device through said top surface.
24. The electronic device of claim 1 , wherein said electronic material comprises a programmable resistance material.
25. The electronic device of claim 1 , wherein said electronic material comprises a phase-change material.
26. The electronic device of claim 1 , wherein said electronic material comprises a chalcogenide material.
27. An array of electronic devices comprising:
a spatially-separated plurality of the electronic devices of claim 1 .
28. The array of claim 27 , further comprising a second dielectric material disposed between said electronic devices.