Thin-film memory system equipped with a thin-film address decoder and memory controller
View Patent ↗An electronic system includes at least one reduced-complexity integrated circuit memory coupled to a memory controller. By reducing the complexity of each integrated circuit memory and concentrating the complexity within the memory controller, overall system costs may be greatly reduced and reliability improved.
1. An electronic system, comprising:
at least one integrated circuit memory, including a thin-film address decoder;
a microprocessor configured to access the at least one integrated circuit memory; and
a memory controller configured to provide access to the at least one integrated circuit memory, the controller including a system interface circuit, a memory interface circuit, and control circuitry configured to transfer data between the system interface circuit and the memory interface circuit.
2. The electronic system of claim 1 , further comprising a transmitter/receiver configured to transmit data from and receive data for the microprocessor or memory.
3. The electronic system of claim 2 , wherein the memory, microprocessor and transmitter/receiver are configured as a cellular telephone.
4. The electronic system of claim 1 , wherein the memory and microprocessor are configured as a handheld entertainment device.
5. The electronic system of claim 1 , wherein the memory includes test registers configured to receive input from an external test device.
6. The electronic system of claim 1 , wherein the memory includes reconfiguration registers configured to receive input from an external test device.
7. The electronic system of claim 1 , wherein the memory includes redundant memory cells configured for mapping into the memory device's memory map under control of an external test device.
8. The electronic system of claim 1 , wherein the memory is configured to receive a reference voltage signal from the memory controller.
9. The electronic system of claim 1 , wherein the memory is configured to transmit an analog representation of a memory cell value to the memory controller for conversion to a digital value.
10. The electronic system of claim 1 , further including a substrate upon which the memory cells and peripheral circuitry are formed, the substrate being a non-single crystal material.
11. The electronic system of claim 10 , wherein the substrate is a ceramic material.
12. The electronic system of claim 10 , wherein the substrate is a fiberglass material.
13. The electronic system of claim 10 , wherein the substrate is a glass material.
14. The electronic system of claim 10 , wherein the substrate is a quartz material.
15. The electronic system of claim 1 , wherein the memory is configured as a solid state drive.