Method of fabricating vertical channel semiconductor device

1. A method of fabricating a semiconductor device, the method comprising:

forming an outer trench, comprising:

a first trench; and

a second trench formed under the first trench, the second trench being formed by etching a substrate;

forming a dielectric layer, which fills the second trench, by performing a thermal oxidation process, such that a width of the second trench is less than a width of the first trench;

forming a gate dielectric layer along a surface of a semiconductor structure comprising the dielectric layer; and

forming a gate electrode, which fills a remaining portion of the outer trench, over the gate dielectric layer.

2. The method of claim 1 , further comprising, before forming the first trench, forming a drain region of a second conductivity type over a lower surface of the substrate.

3. The method of claim 1 , wherein the dielectric layer comprises a silicon oxide layer.

4. The method of claim 1 , wherein the forming of the trench comprises:

forming a hard mask pattern over the substrate;

forming the first trench by etching the substrate using the hard mask pattern as an etch barrier;

forming spacers on sidewalls of the first trench; and

forming the second trench by etching a portion of the substrate which is placed under the first trench, using the hard mask pattern and the spacers as an etch barrier.

5. The method of claim 1 , further comprising, before the forming of the gate dielectric layer, filling a keyhole created in the dielectric layer.

6. The method of claim 1 , further comprising, after the forming of the gate electrode:

forming a well of a first conductivity type in the substrate on each side of the trench;

forming a source region of a second conductivity type in the well;

forming an interlayer dielectric layer on an entire surface of the substrate;

forming a contact hole which exposes the well through the source region, by selectively etching the interlayer dielectric layer and the substrate;

forming a contact region by implanting impurity ions of the first conductivity type into a bottom surface of the contact hole; and

forming a wiring line which fills the contact hole.

7. The method of claim 4 , further comprising, before forming the spacers:

forming a sacrificial dielectric layer over surfaces of the first trench; and

etching partially the sacrificial dielectric layer to be flush with edges of the hard mask pattern.

8. The method of claim 4 , wherein the sacrificial dielectric layer is formed through a thermal oxidation process.

9. The method of claim 4 , further comprising forming a deformation preventing layer over the lower surface of the substrate at the same time as forming the hard mask pattern.

10. The method of claim 7 , wherein the forming of the spacers comprises:

forming a nitride layer over the sacrificial dielectric layer; and

forming the spacers by performing a blanket etching process for the nitride layer.

11. The method of claim 7 , wherein the forming of the gate dielectric layer is implemented on an entire exposed surface of the substrate by performing a thermal oxidation process, after the hard mask pattern, the spacers, and the sacrificial dielectric layer are removed.

12. The method of claim 10 , wherein:

the sacrificial dielectric layer comprises an oxide layer; and

the spacers comprise a nitride layer.

13. The method of claim 11 , further comprising, before the forming of the gate dielectric layer, filling a keyhole created in the dielectric layer.

14. The method of claim 12 , wherein each of the hard mask pattern and the deformation preventing layer is formed as a triple layer in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

15. The method of claim 5 , wherein the filling of the keyhole comprises:

depositing a sacrificial layer along a surface of a structure to fill the keyhole created in the dielectric layer;

converting the sacrificial layer into the same layer as the dielectric layer; and

removing the other portion of the sacrificial layer, except one portion of the sacrificial layer filled in the keyhole.

16. The method of claim 15 , wherein:

the sacrificial layer comprises a silicon layer; and

the sacrificial layer is converted into a silicon oxide layer through a thermal oxidation process performed under an oxygen atmosphere.

17. The method of claim 15 , wherein the sacrificial layer is formed to have a thickness capable of filling the keyhole.

18. The method of claim 16 , wherein the sacrificial layer is formed to have a thickness of approximately 200 Å to approximately 400 Å.

19. The method of claim 6 , wherein a depth of the well is set to be the same as or less than a depth of the first trench from a perspective of an upper surface of the substrate.