Semiconductor device
In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided including a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p-channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
1. A semiconductor device for use in a DC-DC converter, comprising:
a first semiconductor chip including a high-side MOSFET of the DC-DC converter, the high-side MOSFET including a source, a gate and a drain;
a second semiconductor chip including a low-side MOSFET of the DC-DC converter, the low-side MOSFET including a source, a gate and a drain;
a third semiconductor chip including a driver circuit for driving a gate of the high- side MOSFET and a gate of the low-side MOSFET;
an input power supply terminal configured for supplying an input power to the DC-DC converter;
a reference potential supply terminal configured for supplying a reference potential to the DC-DC converter;
an output terminal configured for outputting an output of the DC-DC converter;
an input capacitor coupled to the input power supply terminal and the reference potential supply terminal; and
a resin encapsulator encapsulating the first, second and third semiconductor chips and the input capacitor,
wherein the input capacitor is disposed over the first semiconductor chip and the second semiconductor chip.
2. A semiconductor device according to claim 1 ,
wherein the high-side MOSFET and the low-side MOSFET are electrically coupled in series between the input power supply terminal and the reference potential supply terminal,
wherein a source-to-drain path of the high-side MOSFET is electrically coupled in series between the input power supply terminal and the output terminal, and
wherein a source-to-drain path of the low-side MOSFET is electrically coupled in series between the reference potential supply terminal and the output terminal.
3. A semiconductor device according to claim 1 ,
wherein the resin encapsulator has a top surface and a bottom surface opposite the top surface, and
wherein the input power supply terminal, the reference potential supply terminal and the output terminal are exposed from the bottom surface of the resin body.
4. A semiconductor device according to claim 1 ,
wherein the first semiconductor chip includes a source electrode pad which is electrically coupled to the source of the high-side MOSFET, and
wherein the source electrode pad faces toward the top surface of the resin encapsulator.
5. A semiconductor device according to claim 1 ,
wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and
wherein said one long side of the first semiconductor chip is arranged such that a closest distance between the second semiconductor chip and said one long side is less than a closest distance between the second semiconductor chip and the other long side.
6. A semiconductor device according to claim 1 ,
wherein the gate of the high-side MOSFET is electrically coupled to the driver circuit via a first wire, and
wherein the gate of the low-side MOSFET is electrically coupled to the driver circuit via a second wire.
7. A semiconductor device according to claim 6 ,
wherein the first semiconductor chip has a rectangular shape in plan view, with a pair of long sides and a pair of short sides, and
wherein the first wire is disposed so as to overlap one of the short sides of the first semiconductor chip.
8. A semiconductor device according to claim 1 , wherein the input capacitor is disposed over the first semiconductor chip and the second semiconductor chip to overlap a portion of an upper surface of each of the first and second semiconductor chips when the semiconductor device is viewed in a plane direction.
9. A semiconductor device according to claim 8 , wherein the portion of the upper surface of the first and second semiconductor chips which is overlapped by the input capacitor is less than an entire upper surface of each of the first and second semiconductor chips when viewed in a plane direction.