Replacement gate MOSFET with raised source and drain
A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor.
1. A method of forming a semiconductor structure comprising:
forming a disposable material stack on a semiconductor substrate;
forming a single unitary disposable dielectric spacer on sidewalls of said disposable material stack, wherein a base of the single unitary disposable dielectric spacer is in direct contact with the semiconductor substrate, and wherein said single unitary disposable dielectric spacer is composed of a single material;
forming planar source/drain regions in said semiconductor substrate, said planar source/drain regions laterally surrounding a body region in said semiconductor substrate underlying said disposable material stack;
forming raised source/drain regions laterally spaced from the single unitary disposable dielectric spacer and on said planar source/drain regions;
removing said single unitary disposable dielectric spacer to form a cavity between said disposable material stack and said raised source/drain regions, wherein the removing of the single unitary disposable dielectric spacer exposes peripheral portions of said body region and said planar source/drain regions;
forming source/drain extension regions in said semiconductor substrate by introducing dopants into portions of said body region and said planar source/drain regions through said cavity;
forming a gate-level dielectric layer over said source/drain extension regions, said planar source/drain regions and said raised source/drain regions; and
replacing said disposable material stack with a gate stack including a gate dielectric and a gate electrode.
2. The method of claim 1 , wherein said dopants are introduced into portions of a top semiconductor layer in said substrate, wherein said substrate is a semiconductor-on-insulator (SOI) substrate including a stack, from bottom to top, of a handle substrate, a buried insulator layer, and said top semiconductor layer.
3. The method of claim 2 , wherein said source/drain extension regions are formed within a single crystalline semiconductor portion of said top semiconductor layer, wherein said raised source/drain regions are formed by selective epitaxy with epitaxially alignment to the single crystalline semiconductor portion of said top semiconductor layer.
4. The method of claim 1 , wherein the forming planar source/drain regions is effected by doping portions of said semiconductor substrate, wherein said raised source/drain regions are epitaxially aligned to said planar source/drain regions.
5. The method of claim 4 , wherein said raised source/drain regions are formed by selective epitaxy that deposits a semiconductor material directly on said planar source/drain regions, wherein said semiconductor material does not nucleate on dielectric surfaces during said selective epitaxy.
6. The method of claim 1 , wherein each of said raised source/drain regions contacts a lower portion of an outer sidewall of said single unitary disposable dielectric spacer.
7. The method of claim 1 , wherein said replacing of said disposable material stack with said gate stack is performed by:
forming a gate cavity by removing said disposable material stack;
depositing a gate dielectric layer in said gate cavity; and
forming said gate conductor by depositing at least one gate conductor layer in said gate cavity and removing excess portions of said at least one gate conductor layer above said gate-level dielectric layer.
8. The method of claim 7 , wherein said gate dielectric layer is formed by depositing a dielectric material having a dielectric constant greater than 8.0.
9. The method of claim 7 , wherein said at least one gate conductor layer is formed by depositing a material stack that includes, from bottom to top, a work function metal layer and a metallic layer.
10. The method of claim 1 , further comprising forming a dielectric gate spacer on sidewalls of a gate cavity formed by removing said disposable material stack, wherein vertical surfaces of said gate-level dielectric layer are exposed on said sidewalls of said gate cavity.
11. The method of claim 10 , wherein said dielectric gate spacer is formed by:
depositing a conformal dielectric material layer; and
anisotropically etching horizontal portions of said conformal dielectric material layer, wherein remaining vertical portions of said conformal dielectric material layer is said dielectric gate spacer.
12. The method of claim 1 , wherein said gate stack is laterally spaced from said raised source/drain regions by a lateral dimension that is the same as a lateral dimension of said disposable dielectric spacer.
13. The method of claim 1 , wherein said gate dielectric is a U-shaped gate dielectric that is formed by:
depositing a gate dielectric layer on a semiconductor surface of said semiconductor substrate and sidewalls of said gate-level dielectric layer; and
removing portions of said gate dielectric layer above said gate-level dielectric layer.