Thin film transistor with low trap-density material abutting a metal oxide active layer and the gate dielectric
A metal oxide semiconductor device including an active layer of metal oxide, a layer of gate dielectric, and a layer of low trap density material. The layer of low trap density material is sandwiched between the active layer of metal oxide and the layer of gate dielectric. The layer of low trap density material has a major surface parallel and in contact with a major surface of the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide. A second layer of low trap density material can optionally be placed in contact with the opposed major surface of the active layer of metal oxide so that a low trap density interface is formed with both surfaces of the active layer of metal oxide.
1. A metal oxide semiconductor device comprising:
an active layer of metal oxide with a major surface, the active layer of metal oxide having a bandgap;
a layer of gate dielectric overlying and in parallel abutting engagement with a metal gate contact, the layer of gate dielectric having a first major surface parallel and in contact with the metal gate contact and a second major surface parallel with and opposed to the first major surface, and the layer of gate dielectric comprising oxygen in the bulk and/or at the first major surface, the layer of gate dielectric having a bandgap much larger than the bandgap of the active layer of metal oxide;
a layer of low trap density material positioned between the active layer of metal oxide and the layer of gate dielectric, the layer of low trap density material being thinner than the layer of gate dielectric, the layer of low trap density material having a first major surface parallel and in contact with the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide, the layer of low trap density material having a second major surface parallel and in contact with the second major surface of the layer of gate dielectric to form an interface with the layer of gate dielectric, the layer of low trap density material having a bandgap close to the bandgap of the active layer of metal oxide, and the layer of low trap density material having a low mobility compared to the active layer of metal oxide, and the low trap density material being either amorphous or with grain size 50 nm or less; and
the active layer of metal oxide, the layer of gate dielectric, and the layer of low trap density material are all included in one of a top gate, bottom source/drain type of device, a top gate, top source/drain type of device, a bottom gate, bottom source/drain type of device, and a bottom gate, top source/drain type of device.
2. A metal oxide semiconductor device as claimed in claim 1 wherein the layer of low trap density material includes one of TiO, Ta 2 O 5 , NbO, V 2 O 5 , ScO 2 ,Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 5 , MoO, CrO SrTiO 3 , SrNbO 3 , lead zirconate titanate (PZT), barium strontium titanate (BST), and a mixture oxide comprising more than one of the materials or the metal-oxygen bonds above.
3. A metal oxide semiconductor device as claimed in claim 1 wherein the layer of low trap density material includes one of a group of organic materials including Alq3: tris (8-hydroxyquinolinolato) aluminum (III) Balq3: Bis(2-methyl-8-quinolineolate)-4-(phenylphenolato) aluminium, Bepq2: Bis(10-hydroxybenzo[h]quinolinato) Beryllium, PBD: 2-(4-Biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole, TAZ: 3-(4-Biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole, Bphen: 4,7-Diphenyl-1,10-phenyanthroline, C60, C70, nanotube, and other fullerene molecules, Graphene molecules, PMGI (polymethylglutarimide), BCB (bis-benzocyclobutene), SU-8, and PMMA (Poly(methyl methacrylate).
4. A metal oxide semiconductor device comprising:
an active layer of metal oxide with a major surface, the active layer of metal oxide having a bandgap;
a layer of gate dielectric overlying and in parallel abutting engagement with a metal gate contact, the layer of gate dielectric having a first major surface parallel and in contact with the metal gate contact and a second major surface parallel with and opposed to the first major surface, and the layer of gate dielectric comprising oxygen in the bulk and/or at the first major surface, the layer of gate dielectric having a bandgap much larger than the bandgap of the active layer of metal oxide;
a layer of low trap density material positioned between the active layer of metal oxide and the layer of gate dielectric, the layer of low trap density material being thinner than the layer of gate dielectric, the layer of low trap density material having a first major surface parallel and in contact with the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide, the layer of low trap density material having a second major surface parallel and in contact with the second major surface of the layer of gate dielectric to form an interface with the layer of gate dielectric, and the layer of low trap density material having a bandgap close to the bandgap of the active layer of metal oxide.
5. A metal oxide semiconductor device as claimed in claim 4 wherein the layer of low trap density material has a low mobility compared with the active layer of metal oxide, and the low trap density material is either amorphous or with grain size 50 nm or less.
6. A metal oxide semiconductor device as claimed in claim 4 wherein the layer of low trap density material includes one of TiO, Ta 2 O 5 , NbO, V 2 O 5 , ScO 2 , Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 5 , MoO, CrO SrTiO 3 , SrNbO 3 , lead zirconate titanate (PZT), barium strontium titanate (BST), and a mixture oxide comprising more than one of the materials or the metal-oxygen bonds above.
7. A metal oxide semiconductor device as claimed in claim 4 wherein the layer of low trap density material includes one of a group of organic materials including Alq3: tris (8-hydroxyquinolinolato) aluminum (III) Balq3: Bis(2-methyl-8-quinolineolate)-4-(phenylphenolato) aluminium, Bepq2: Bis(10-hydroxybenzo[h]quinolinato) Beryllium, PBD: 2-(4-Biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole, TAZ: 3-(4-Biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole, Bphen: 4,7-Diphenyl-1,10-phenyanthroline, C60, C70, nanotube, and other fullerene molecules, Graphene molecules, PMGI (polymethylglutarimide), BCB (bis-benzocyclobutene), SU-8, and PMMA (Poly(methyl methacrylate).
8. A metal oxide semiconductor device as claimed in claim 4 wherein the layer of low trap density material has a thickness in a range of 5 nm to 50 nm.
9. A metal oxide semiconductor device as claimed in claim 4 wherein the active layer of metal oxide has an opposed major surface, and the device further includes a second layer of low trap density material having a major surface parallel and in contact with the opposed major surface of the active layer of metal oxide to form a low trap density interface with the opposed major surface of the active layer of metal oxide.
10. A metal oxide semiconductor device as claimed in claim 4 wherein the active layer of metal oxide, the layer of gate dielectric, and the layer of low trap density material are all included in one of a top gate, bottom source/drain type of device, a top gate, top source/drain type of device, a bottom gate, bottom source/drain type of device, and a bottom gate, top source/drain type of device.
11. A metal oxide semiconductor device comprising:
an active layer of metal oxide with a major surface;
a layer of gate dielectric overlying and in parallel abutting engagement with a metal gate contact, the layer of gate dielectric having a first major surface parallel and in contact with the metal gate contact and a second major surface parallel with and opposed to the first major surface, and the layer of gate dielectric comprising oxygen in the bulk and/or at the first major surface; and
a layer of low trap density material positioned between the active layer of metal oxide and the layer of gate dielectric, the layer of low trap density material being thinner than the layer of gate dielectric, the layer of low trap density material having a first major surface parallel and in contact with the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide and a second major surface in parallel and in contact with the second major surface of the layer of gate dielectric.
12. A metal oxide semiconductor device as claimed in claim 11 wherein the active layer of metal oxide has a bandgap and the layer of gate dielectric has a bandgap much larger than the bandgap of the active layer of metal oxide, and the layer of low trap density material has a bandgap close to the bandgap of the active layer of metal oxide, and the low trap density material is either amorphous or with grain size 50 nm or less.
13. A metal oxide semiconductor device as claimed in claim 11 wherein the layer of low trap density material has a low mobility compared with the active layer of metal oxide.
14. A metal oxide semiconductor device as claimed in claim 11 wherein the layer of low trap density material includes one of TiO, Ta 2 O 5 , NbO, V 2 O 5 , ScO 2 , Y 2 O 3 , ZrO 2 , HfO 2 , La 2 O 5 , MoO, CrO SrTiO 3 , SrNbO 3 , lead zirconate titanate (PZT), barium strontium titanate (BST), and a mixture oxide comprising more than one of the materials or the metal-oxygen bonds above.
15. A metal oxide semiconductor device as claimed in claim 11 wherein the layer of low trap density material includes one of a group of organic materials including Alq3: tris (8-hydroxyquinolinolato) aluminum (III), Balq3: Bis(2-methyl-8-quinolineolate)-4-(phenylphenolato) aluminium, Bepq2: Bis(10-hydroxybenzo[h]quinolinato) Beryllium, PBD: 2-(4-Biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole, TAZ: 3-(4-Biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole, Bphen: 4,7-Diphenyl-1,10-phenyanthroline, C60, C70, nanotube, and other fullerene molecules, Graphene molecules, PMGI (polymethylglutarimide), BCB (bis-benzocyclobutene), SU-8, and PMMA (Poly(methyl methacrylate).
16. A metal oxide semiconductor device as claimed in claim 11 wherein the active layer of metal oxide includes a layer of semiconductor amorphous metal oxide.
17. A metal oxide semiconductor device as claimed in claim 11 wherein the active layer of metal oxide has an opposed major surface, and the device further including a second layer of low trap density material having a major surface parallel and in contact with the opposed major surface of the active layer of metal oxide to form a low trap density interface with the opposed major surface of the active layer of metal oxide.
18. A metal oxide semiconductor device as claimed in claim 11 wherein the active layer of metal oxide, the layer of gate dielectric, and the layer of low trap density material are all included in one of a top gate, bottom source/drain type of device, a top gate, top source/drain type of device, a bottom gate, bottom source/drain type of device, and a bottom gate, top source/drain type of device.
19. A metal oxide semiconductor device as claimed in claim 11 wherein the layer of low trap density material has a thickness in a range of 5 nm to 50 nm.