Systems, circuits and methods for an analog echo canceller with interpolating output
A method and system are described for canceling an echo signal in analog domain with adaptive filters working in digital domain. In one embodiment a system includes an analog-to-digital converter (ADC) sampling at two different phases to generate a first error signal and a second error signal having different phases. The ADC operates at a frequency significantly lower than the frequency at which the individual filters run. The first adaptive filter unit and a second adaptive filter unit are independently trained with the first and second error signals. respectively. The first and second adaptive filter units generate echo estimate signals used to cancel the echo signal.
1 . A system for echo cancelation, comprising:
a single error analog-to-digital converter (EADC) for generating a plurality of error signals, each of the error signals having a different phase;
a plurality of adaptive filters, coupled to the EADC, for generating a plurality of digital echo estimate signals, each of the adaptive filters configured to be trained by one of the error signals having a different phase; and
a multiplexer, coupled to the adaptive filters, for interleaving the plurality of error signals and for generating a combined digital echo estimate signal from the interleaved error signals.
2 . The system of claim 1 , wherein each of the adaptive filters is trained by one of a plurality of least means squared (LMS) units that receives one of the error signals and generates tap coefficients for a coefficient update block for one of the adaptive filters.
3 . The system of claim 1 , wherein the plurality of adaptive filters comprises a poly phase implementation of a filter bank.
4 . The system of claim 3 , wherein the poly phase implementation of a filter bank comprises a plurality of sub-filters that operate in parallel, each of the sub-filters having a different sampling point of an input signal.
5 . The system of claim 1 , wherein each adaptive filter receives an identical input sample signal, each of the digital echo estimate signals generated by one of the adaptive filters sampling the identical input sample signal, each of the adaptive filters having a different sampling time.
6 . The system of claim 1 , further comprising a plurality of least means squared (LMS) units, each LMS unit comprising a plurality of latches, each latch receiving a different clock signal for updating a coefficient for one of the adaptive filters.
7 . The system of claim 1 , further comprising a digital-to-analog converter (DAC), coupled to the multiplexer, for receiving the combined digital echo estimate signal and for generating an analog signal estimating an echo signal.
8 . A method for echo cancelation, comprising:
generating a plurality of error signals, each of the error signals having a different phase;
generating a plurality of digital echo estimate signals from a plurality of adaptive filters, each of the adaptive filters configured to be trained by one of the error signals having a different phase;
interleaving the plurality of error signals; and
generating a combined digital echo estimate signal from the interleaved error signals.
9 . The method of claim 8 , wherein each of the plurality of adaptive filters is trained by one of a plurality of least means squared (LMS) units that receives one of the error signals and generates tap coefficients for a coefficient update block for one of the adaptive filters.
10 . The method of claim 8 , wherein the plurality of adaptive filters comprises a poly phase implementation of a filter bank.
11 . The method of claim 8 , wherein the poly phase implementation of a filter bank comprises a plurality of sub-filters that operate in parallel, each of the sub-filters having a different sampling point of an input signal.
12 . The method of claim 8 , wherein each adaptive filter receives an identical input sample signal, each of the digital echo estimate signals generated by one of the adaptive filters sampling the identical input sample signal, each of the adaptive filters having a different sampling time.
13 . The method of claim 8 , further comprising a plurality of least means squared (LMS) units, each LMS unit comprising a plurality of latches, each latch receiving a different clock signal for updating a coefficient for one of the adaptive filters.
14 . The method of claim 8 , further comprising a digital-to-analog converter (DAC) for receiving the combined digital echo estimate signal and for generating an analog signal estimating an echo signal.
15 . A circuit for echo cancelation, comprising:
a single error analog-to-digital converter (EADC) for generating a plurality of error signals, each of the error signals having a different phase;
a filter bank comprising a plurality of adaptive filters, coupled to the EADC, each adaptive filter for generating a plurality of digital echo estimate signals and to be configured to be trained by one of the error signals having a different phase; and
a multiplexer, coupled to the adaptive filters, for interleaving the plurality of error signals and for generating a combined digital echo estimate signal from the interleaved error signals.
16 . The circuit of claim 15 , wherein each of the adaptive filters is trained by one of a plurality of least means squared (LMS) units that receives one of the error signals and generates tap coefficients for a coefficient update block for one of the adaptive filters.
17 . The circuit of claim 15 , wherein the filter bank comprises a poly phase implementation of filters.
18 . The circuit of claim 17 , wherein the poly phase implementation of a filter bank comprises a plurality of sub-filters that operate in parallel, each of the sub-filters having a different sampling point of an input signal.
19 . The circuit of claim 15 , wherein each adaptive filter receives an identical input sample signal, each of the digital echo estimate signals generated by one of the adaptive filters sampling the identical input sample signal, each of the adaptive filters having a different sampling time.
20 . The circuit of claim 15 , further comprising a plurality of least means squared (LMS) units, each LMS unit comprising a plurality of latches, each latch receiving a different clock signal for updating a coefficient for one of the adaptive filters.