Method for testing cryptographic circuits, secured cryptographic circuit capable of being tested, and method for wiring such circuit

1. A method for testing correct operation of a cryptography circuit having a secret and including registers and logic gates interconnected by a set of nodes, said method comprising:

performing a differential power analysis to predict activity of each node in the set of nodes;

acquiring measurements of power-consumption traces at each node in the set of nodes as a function of test signal vectors at an input of the cryptography circuit;

determining a rate of activity of each node in the set of nodes based on the measurements of the power-consumption traces at the set of nodes; and

determining that a node in the set of nodes is operating correctly when the determined activity of the node is positively correlated with the predicted activity of the node.

2. The method as claimed in claim 1 , wherein the differential power analysis is carried out with a known secret, and the secret of the cryptography circuit is customized after the test.

3. The method as claimed in claim 1 , wherein, the cryptography circuit is secure and comprises a first half-circuit associated with a second half-circuit operating in complementary logic, wherein an electric power supply of the first half-circuit is separated from an electric power supply of the second half-circuit, the differential power analysis being carried out in parallel on each half-circuit, the two electronic power supplies being combined into one and same electric power supply after the test.

4. The method as claimed in claim 3 , wherein components of the first half-circuit are connected via power supply lines to a first voltage source and components of the second half-circuit are powered via power supply lines to a second voltage source, the two voltage sources being distinct, and the power supply lines being connected after the test.

5. The method as claimed in claim 4 , wherein the components of the first half-circuit are connected via ground lines to a first reference potential and the components of the second half-circuit are powered via ground lines to a second reference potential, the two reference potentials being separated, and the ground lines being connected after the test.

6. The method as claimed in claim 3 , wherein the two electronic power supplies are combined after the acquiring step.

7. The method as claimed in claim 1 , wherein the acquisition of the measurements of the power-consumption traces is carried out only on the registers.

8. A secure cryptography circuit comprising:

a first half-circuit;

a second half-circuit operating in complementary logic with the first half-circuit;

a first electric power supply path assigned to the first half-circuit; and

a second electric power supply path assigned to the second half-circuit, wherein:

the second electric power supply path is different from the first electric power supply path,

the first half-circuit and the second half-circuit are tested by a differential power analysis independently and in parallel, and

the first electric power supply path and the second electric supply path are configured to be short-circuited after testing of the first half-circuit and the second half-circuit.

9. The circuit as claimed in claim 8 , wherein:

the first electric power supply path comprises a first peripheral conducting ring configured to be connected to a first voltage source and electrically connected to power supply lines of components of the first half-circuit;

the second electric power supply path comprises a second peripheral conducting ring configured to be connected to a second voltage source and electrically connected to power supply lines of components of the second half-circuit; and

the two peripheral conducting rings are configured to be short-circuited.

10. The circuit as claimed in claim 9 , wherein the peripheral conducting rings are connected together by antifuses, the short circuit between the two peripheral conducting rings being produced by melting of the antifuses.

11. The circuit as claimed in claim 8 , wherein:

the first electric power supply path comprises a first peripheral conducting ring configured to be connected to a first ground potential and electrically connected to ground lines of components of the first half-circuit;

the second electric power supply path comprises a second peripheral conducting ring configured to be connected to a second ground potential and electrically connected to ground lines of components of the second half-circuit; and

the two peripheral conducting rings are configured to be short-circuited.

12. The circuit as claimed in claim 8 , wherein the electric power supply paths are connected together by antifuse technology allowing transition from an isolating state to a conducting state in an irreversible manner after melting.

13. The circuit as claimed in claim 8 , wherein the secure cryptography circuit comprises only two electric supply paths.

14. A method of wiring power supplies of a secure cryptography circuit including a first half-circuit associated with a second half-circuit operating in complementary logic, the method comprising:

assigning a first electric power supply path to the first half-circuit; and

assigning a second electric power supply path to the second half-circuit, wherein:

the second electric power supply path is different from the first electric power supply path,

the first half-circuit and the second half-circuit are tested by a differential power analysis independently and in parallel, and

the first electric power supply path and the second electric supply path are configured to be short-circuited after testing of the first half-circuit and the second half-circuit.

15. The method as claimed in claim 14 , wherein the secure cryptography circuit comprises only two electric supply paths.