IP Library Granted Patent US 8,422,837
Granted Patent B2
US 8,422,837 · App. 12/919,546 · Granted Apr 16, 2013

Semiconductor device

Inventors: Kenichi Nishi (Tokyo, JP); Junichi Fujikata (Tokyo, JP); Jun Ushida (Tokyo, JP); Daisuke Okamoto (Tokyo, JP)
Assignee: NEC Corporation
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Quick Facts
Patent No.
US 8,422,837
App. No.
12/919,546
Granted
Apr 16, 2013
Kind
B2
Abstract

A semiconductor device comprises a semiconductor layer having a semiconductor integrated circuit, which is for processing an electrical signal, on a semiconductor substrate and an optical interconnect layer for transmitting an optical signal are joined. Control of modulation of the optical signal transmitted in the optical interconnect layer is performed by an electrical signal from the semiconductor layer, and an electrical signal generated by reception of light in the optical interconnect layer is transmitted to the semiconductor layer. The optical interconnect layer is disposed on the underside of the semiconductor substrate.

Claims (23)

1. A semiconductor device, comprising:

semiconductor layer having a semiconductor integrated circuit, which is for processing an electrical signal, on an upper side of a semiconductor substrate and an optical interconnect layer for transmitting an optical signal are joined,

control of modulation of the optical signal transmitted in said optical interconnect layer being performed by the electrical signal from said semiconductor layer, and an electrical signal generated by reception of light in said optical interconnect layer being transmitted to said semiconductor layer;

wherein said optical interconnect layer is disposed on an underside of the opposite side to the upper side of said semiconductor substrate,

wherein said semiconductor integrated circuit is formed to have an electrode pad for supplying power to said semiconductor integrated circuit externally or for externally extracting an electrical signal from said semiconductor integrated circuit, on the opposite side to the said semiconductor substrate side of said semiconductor integrated circuit.

2. A semiconductor device according to claim 1 , wherein said optical interconnect layer is bonded to the underside of the semiconductor substrate.

3. A semiconductor device according to claim 1 , wherein said semiconductor integrated circuit has an interconnect area for transmitting an electrical signal to be converted to an optical signal; and

said semiconductor substrate has a through-hole leading from the underside of said semiconductor substrate to said interconnect area, an electrical conductor electrically connected to an interconnect of said interconnect area is formed within said through-hole, and a distal end of said electrical conductor on the underside of said semiconductor substrate has a pad portion for being electrically connected to said optical interconnect layer.

4. A semiconductor device according to claim 3 , wherein the interior of said through-hole has an insulator between said semiconductor substrate and said electrical conductor.

5. A semiconductor device according to claim 3 , wherein, on the underside of said semiconductor substrate, the diameter of said through-hole is relatively large in comparison with the diameter thereof on the upper side of said semiconductor substrate.

6. A semiconductor device according to claim 3 , wherein said electrical conductor is a metal via structure formed by plating from the underside of said semiconductor substrate.

7. A semiconductor device comprising:

a semiconductor layer having a semiconductor integrated circuit, which is for processing an electrical signal, on a semiconductor substrate and an optical interconnect layer for transmitting an optical signal are joined,

control of modulation of the optical signal transmitted in said optical interconnect layer being performed by the electrical signal from said semiconductor layer, and an electrical signal generated by reception of light in said optical interconnect layer being transmitted to said semiconductor layer;

wherein said optical interconnect layer is disposed on the underside of said semiconductor substrate,

wherein said semiconductor integrated circuit has an interconnect area for transmitting an electrical signal to be converted to an optical signal; and

said semiconductor substrate has a bottomed hole formed so as to thin said semiconductor substrate from the underside thereof, and has a through-hole, which leads to said interconnect area, within an area on the bottom of said bottomed hole, an insulator is embedded within said bottomed hole and said through-hole, a hole leading from the underside to said interconnect area is formed in said insulator, an electrical conductor electrically connected to an interconnect of said interconnect area is formed within said hole, and a distal end of said electrical conductor on the underside of said insulator has a pad portion for being electrically connected to said optical interconnect layer.

8. A semiconductor device, comprising:

a semiconductor layer having a semiconductor integrated circuit, which is for processing an electrical signal, on a semiconductor substrate and an optical interconnect layer for transmitting an optical signal are joined,

control of modulation of the optical signal transmitted in said optical interconnect layer being performed by the electrical signal from said semiconductor layer, and an electrical signal generated by reception of light in said optical interconnect layer being transmitted to said semiconductor layer;

wherein said optical interconnect layer is disposed on the underside of said semiconductor substrate,

wherein the interior of said through-hole has an insulator between said semiconductor substrate and said electrical conductor,

wherein said insulator is composed of an oxide film of a main constituent element of said semiconductor substrate or an organic compound.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2010
From: NISHI, KENICHI; FUJIKATA, JUNICHI; USHIDA, JUN; OKAMOTO, DAISUKE
To: NEC CORPORATION
Reel/Frame 024890/0799 →
Priority Claims (1)
JP 2008-047736 · Feb 28, 2008 · national
Continuity (1)
Related Publication 20100320496A1 · Dec 23, 2010